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Observer baileyji
Observer
271 Views
Registered: ‎02-20-2019

AXIS hls::stream fails with incompatible types when using side channel data and structs with arrays

Hi Folks,

   For the life of me I can not get an axi stream working that contains and array and side channel data. Regardless of how I mix and match DATA_PACK compilation complains:

ERROR: [XFORM 203-801] Interface read on 'i_stream.V.data.iorq.V' (bin_to_res_buffer/forum_post.cpp:29) has incompatible types. Possible cause(s): data pack is only applied on source(port) or destination(variable).

Even though it reports:

INFO: [XFORM 203-1101] Packing variable 'i_stream.V.data.iorq.V' (bin_to_res_buffer/forum_post.cpp:29) into a 256-bit variable.
INFO: [XFORM 203-1101] Packing variable 'q_stream.V.data.iorq.V' (bin_to_res_buffer/forum_post.cpp:29) into a 256-bit variable.
INFO: [XFORM 203-1101] Packing variable 'in_ivals.data.iorq.V' (bin_to_res_buffer/forum_post.cpp:51) into a 256-bit variable.
INFO: [XFORM 203-1101] Packing variable 'in_qvals.data.iorq.V' (bin_to_res_buffer/forum_post.cpp:51) into a 256-bit variable.

Even this is confusing because as I understand it since I've assigned the ports as axi streams, with or without side channels data_pack should be automatically applied to the .data member (per, I beleive pg902).

Any thoughts on how I can get this working?

 

#include "ap_int.h"
#include "hls_stream.h"
#include <complex>

#define N_PFB_BINS_PER_CLK 16
#define resid_t ap_uint<11>  //must match bit width of N_RESONATORS
#define cycleid_t ap_int<8>  //must match bit width of N_CYCLES
typedef std::complex< ap_uint<16> > iq_t;

typedef struct resIQ_stream_t{
 struct {
	 iq_t val;
 } data;
 resid_t user;
} resIQ_stream_t;

typedef struct opfb_stream_t{
    struct {
    	ap_uint<16> iorq[N_PFB_BINS_PER_CLK];
    } data;
    cycleid_t user;
} opfb_stream_t;

typedef hls::stream<opfb_stream_t> in_t;
typedef hls::stream<resIQ_stream_t> out_t;

void forum_example(in_t &i_stream, in_t &q_stream,
		out_t &out0, out_t &out1, out_t &out2, out_t &out3,
		out_t &out4, out_t &out5, out_t &out6, out_t &out7) {

#pragma HLS PIPELINE II=1
#pragma HLS INTERFACE axis port=i_stream
#pragma HLS INTERFACE axis port=q_stream
#pragma HLS INTERFACE axis port=out0
#pragma HLS INTERFACE axis port=out1
#pragma HLS INTERFACE axis port=out2
#pragma HLS INTERFACE axis port=out3
#pragma HLS INTERFACE axis port=out4
#pragma HLS INTERFACE axis port=out5
#pragma HLS INTERFACE axis port=out6
#pragma HLS INTERFACE axis port=out7
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS DATA_PACK variable=i_stream
#pragma HLS DATA_PACK variable=q_stream

	// Working variables
	opfb_stream_t in_ivals, in_qvals;
	resIQ_stream_t out_val;
	iq_t val;

#pragma HLS DATA_PACK variable=in_ivals.data
#pragma HLS DATA_PACK variable=in_qvals.data

	// Cache
	static iq_t bin_iq_cache[4096];
	static resid_t id_ndx=0; 

	// Fetch the outbound rID IQs for this cycle
	for (int i=0; i<8; i++){
		out_val.data.val=bin_iq_cache[id_ndx+i];
		out_val.user=id_ndx+i;
	    switch(i) {
	        case 0: out0<<out_val; break;
	        case 1: out1<<out_val; break;
	        case 2: out2<<out_val; break;
	        case 3: out3<<out_val; break;
	        case 4: out4<<out_val; break;
	        case 5: out5<<out_val; break;
	        case 6: out6<<out_val; break;
	        case 7: out7<<out_val; break;
	    }
	}
	if (id_ndx == 2040) id_ndx = 0;
	else id_ndx += 8;

	//Cache the new vals
	i_stream>>in_ivals;
	q_stream>>in_qvals;
	for (int i=0; i<N_PFB_BINS_PER_CLK; i++){
		val.real(in_ivals.data.iorq[i]);
		val.imag(in_qvals.data.iorq[i]);
		bin_iq_cache[in_ivals.user*N_PFB_BINS_PER_CLK+i] = val;
	}
}
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1 Reply
Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎09-04-2017

Re: AXIS hls::stream fails with incompatible types when using side channel data and structs with arrays

@baileyji   This seems to be an issue with HLS. Have reported this to our Team to see if this can be addressed in a future release

As a workaround, you can use ap_fifo interface for i_stream and q_stream if that suits your design requirements.

Thanks,

Nithin

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