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rmanor
Observer
Observer
1,362 Views
Registered: ‎05-18-2015

AXIS output values when _TVALID = 0

Is it possible to control the output values of _TKEEP , _TUSER , _TDATA , _TLAST when the _TVALID is signal is set to 0

 

Currently, those outputs all showing X (assigned 'bx in verilog) when _TVALID is 0 and this cause some integration/simulation problems with other modules expecting only 1 or 0 values.

 

..... top (........, hls::stream<outAxis> &o_out, ............) {
#pragma HLS INTERFACE axis off port=o_out

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chrisz
Xilinx Employee
Xilinx Employee
1,301 Views
Registered: ‎05-06-2008

Hello @rmanor,

 

I have not seen this in the simulation results before, so can you provide the code or example code to help me investigate this issue?

 

Thanks,
Chris

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rmanor
Observer
Observer
1,286 Views
Registered: ‎05-18-2015

template<int D>
struct ap_axis_r{
   ap_axis_r():data(0),keep(0xFF),last(0),user(0){}
   ap_uint<D> data;
   ap_uint<(D+7)/8> keep;
   ap_uint<1> last;
   ap_uint<1> user;
};

typedef ap_axis_r<64> outAxis;

 

ap_uint<1> top(........., hls::stream<outAxis> &o_out, ............) {
#pragma HLS INTERFACE axis off port=o_out
 

Verilog after Synthesis:

always @ (*) begin
   if (((1'b1 == ap_CS_fsm_state45) | (1'b1 == ap_CS_fsm_state46) | .......... ))) begin
      o_out_TLAST = 1'd1;

   end

   else if (((1'b1 == ap_CS_fsm_state43) | (1'b1 == ap_CS_fsm_state42) | .......... ))) begin
      o_out_TLAST = 1'd0;
   end

   else begin
      o_out_TLAST = 'bx;
   end
end

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