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Registered: ‎10-18-2013

Access peripherals from HLS via AXI Master interface

Dear forum users,


I am rather new to FPGAs and I have started working with an AC701 evaluation board using Vivado and Vivado HLS.
My goal is to set up a system that can process data stored in DDR3 memory. The idea is to use a microblaze system for management and a custom IP created by Vivado HLS that performs the processing.



Let me describe what I have running:

There is a MicroBlaze connected to various peripherals (timer, UARTlite, GPIO) via a AXI interconnect (AI1). There is a nother AXI interconnect (AI2) which is connected to AI2. AI2 has one free slave port where I would like to connect the custom IP. The mig controlling the DDR3 SO-DIMM is connected to AI2.

I can export this design to SDK. In the XMD console I can read/write to the peripheral, e.g. GPIO and UARTlite. I can also add projects using xilkernel and run applications like "hello world" and "memory tests". This works fine.


Now I created a simple project in vivado HLS and the code looks like this:


void foo (int * npair)





I have set the interface of npair to ap_bus and the resource to AXI4M. I can export this IP with a AXI4 master interface. I imported the IP into vivado and connected the AXI master to AI2. Of course I connected the clock, reset and start.

The problem is that I can not tell if my setup is working.


So here are my questions:


How should I configure the the custom IP in vivado? When I oopen the "re-customize IP" dialog I don't know what to put in "base address of target slave" and "user value" and the others.

I guess *npair will point to "base address of target slave"?!? but I can not find the value of 15 at that address when I set "base address of target slave"=0x80000000 which is the address of the DDR3. The DDR3 is the only component visible to the custom IP as only the DDR3 is connected to AI2.


Could anyone help me with this?



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Registered: ‎10-18-2013



I got the setup working but unfortunately I do not know what the problem was. It might be the order in which I connecte the elements to the AXI bus.




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