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Observer sbuschjaeger
Observer
4,128 Views
Registered: ‎07-29-2015

Access variable parts of integers in C++ code

Hi,

 

I've written some C++ code operating on single bits using bitmasks and shift registers. For example, when implementing a binary tree, I can encode every node with lets say 60 bits. Then the tree is saved using standard integer numbers and I could access the information in the nodes with bitmasks, e.g. for the left child of node pI I use a function like:

 

static const unsigned long long tree0[141]={72304694089285632ull,...}
inline unsigned int getLeftChild(unsigned int pI){ return (unsigned int)((tree0[pI] & 0x7f800000000000) >> 47); }

 

I use the bitmask 

0x7f800000000000

to access a specific part of the integer and then shift it into the right direction. From my point of view, on the FPGA the AND + SHIFT operation boils down to a simple rewiring. I just access e.g. 16 bit starting in the middle of a bitstring. 

However, HLS does not seem to recognize this structure. Is there a way to HLS whats going on here? 

Would it be better to use the provided arbitrary precision types?

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2 Replies
Teacher muzaffer
Teacher
4,105 Views
Registered: ‎03-31-2012

Re: Access variable parts of integers in C++ code

yes, with ap_int or ap_fixed you can access individual bit slices quite easily.

 

Also why do you say "HLS does not seem to recognize this structure" ? What evidence have you seen that it's not recognized (and BTW, what does it mean to not recognize? Does it not work? or does it produce slow/large code?). It's sometimes difficult to figure out what code HLS is generating for a certain coding style. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Observer sbuschjaeger
Observer
4,092 Views
Registered: ‎07-29-2015

Re: Access variable parts of integers in C++ code

Thanks for your quick answer!

I re-implemented my tree structure using the ap_int types and got roughly the same performance estimate by SDSoC. Both implementation need around 20k clock cycles which seems way too much in my opinion. However, starting vivado hls from SDSoC and re-synthesizing the code gives me an estimate around 1k clock cycles, which seems way more reasonable to me.

I use SDSoC 2016.2 on ubuntu 14.04 with a zedboard.

Maybe I misinterpret the estimate of SDSoC? Or maybe there is some option I did not check?

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