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@datang
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Registered: ‎07-28-2017

Active time of sub-function when it runs on FPGA

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Hi,

I suppose I have function top. Inside top function, I call sub-function A. I want to determine active time of sub-function A(when function A starts, when it stops)  when function top run on FPGA. what should I do with HLS code?

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baltam
Contributor
Contributor
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Registered: ‎03-13-2017

@datang wrote:

But ap_start and ap_done are only generated for function top, and function A doesnt have any signal as ap_done, ap_start.  


Not true. It depends on how you have defined the interface of A. 
Please look at the following code snips.

The following C source comes from a real project where the interface protocol is the default one ap_ctrl_hs (_hs here means 'hand-shaking'). 
The TOP function is RunMMTOneSL() , the inner function  is RunMMTOneMC()

 

 

 

#include...
// TOP HLS function
void RunMMTOneSL( WireShift_t corrFirstWire, .... )
{
    ...
    #pragma HLS ARRAY_PARTITION ....
    ...
    for ( MCellIdx_t iMacroCell = 0; iMacroCell < MAX_MACROCELLS; ++iMacroCell )
    {
      #pragma HLS UNROLL
      .....
      timePMCell[ iMacroCell ] = RunMMTOneMC( cntHits[ iMacroCell ], .... );
    }
}

// Inner function
TimeTDC_t RunMMTOneMC( b5_Idx_t cntHits,.... )
{
 ...<body of function> ...
}

This has been mapped in VHDL  by HLS as follow

 

-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RunMMTOneSL is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    corrFirstWire_V : IN STD_LOGIC_VECTOR (2 downto 0);
....
);
end;

architecture behav of RunMMTOneSL is 
    attribute CORE_GENERATION_INFO : STRING;
    attribute CORE_GENERATION_INFO of behav : architecture is
...
component RunMMTOneSL_RunMMTOneMC IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; cntHits_V : IN STD_LOGIC_VECTOR (4 downto 0); ... ); end component; begin grp_RunMMTOneSL_RunMMTOneMC_fu_1614 : component RunMMTOneSL_RunMMTOneMC port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_start, ap_done => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_done, ap_idle => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_idle, ap_ready => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_ready, cntHits_V => cntHits_0_V, .... ); ....
.... end behav;

 

As fast check you could try to change the block-level I/O protocol of function A and check the interface summary on synthesis report.

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u4223374
Advisor
Advisor
2,883 Views
Registered: ‎04-26-2015

HLS can tell you this in the synthesis report.

 

If you actually want to measure it at runtime, that's going to be tricky - time to connect a debug core and start digging through the HDL code.

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@datang
Newbie
Newbie
2,847 Views
Registered: ‎07-28-2017

I know HLS can report about latency of function top. when function A access to DDRAM, report about latency of function A is incorrect. I want to know when function A starts, when it stops.

I read HDL code which is generated by HLS, and it has many states, so I dont know where function A starts to tricky - time.

with HSL code, what can I do?  

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baltam
Contributor
Contributor
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Registered: ‎03-13-2017

@datang wrote:

... I want to know when function A starts, when it stops.


In simulation, if the block-level handshakes of the function A is enabled or you can enable it, then you should be able to measure the elapsed time between ap_start and ap_done signals. If you want to measure them in a real system with a scope, you have to add 2 signals to the TOP I/O interface and active them at the beginning and at the end of the A function.

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@datang
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Registered: ‎07-28-2017

But ap_start and ap_done are only generated for function top, and function A doesnt have any signal as ap_done, ap_start.  

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baltam
Contributor
Contributor
4,672 Views
Registered: ‎03-13-2017

@datang wrote:

But ap_start and ap_done are only generated for function top, and function A doesnt have any signal as ap_done, ap_start.  


Not true. It depends on how you have defined the interface of A. 
Please look at the following code snips.

The following C source comes from a real project where the interface protocol is the default one ap_ctrl_hs (_hs here means 'hand-shaking'). 
The TOP function is RunMMTOneSL() , the inner function  is RunMMTOneMC()

 

 

 

#include...
// TOP HLS function
void RunMMTOneSL( WireShift_t corrFirstWire, .... )
{
    ...
    #pragma HLS ARRAY_PARTITION ....
    ...
    for ( MCellIdx_t iMacroCell = 0; iMacroCell < MAX_MACROCELLS; ++iMacroCell )
    {
      #pragma HLS UNROLL
      .....
      timePMCell[ iMacroCell ] = RunMMTOneMC( cntHits[ iMacroCell ], .... );
    }
}

// Inner function
TimeTDC_t RunMMTOneMC( b5_Idx_t cntHits,.... )
{
 ...<body of function> ...
}

This has been mapped in VHDL  by HLS as follow

 

-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RunMMTOneSL is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    corrFirstWire_V : IN STD_LOGIC_VECTOR (2 downto 0);
....
);
end;

architecture behav of RunMMTOneSL is 
    attribute CORE_GENERATION_INFO : STRING;
    attribute CORE_GENERATION_INFO of behav : architecture is
...
component RunMMTOneSL_RunMMTOneMC IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; cntHits_V : IN STD_LOGIC_VECTOR (4 downto 0); ... ); end component; begin grp_RunMMTOneSL_RunMMTOneMC_fu_1614 : component RunMMTOneSL_RunMMTOneMC port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_start, ap_done => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_done, ap_idle => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_idle, ap_ready => grp_RunMMTOneSL_RunMMTOneMC_fu_1614_ap_ready, cntHits_V => cntHits_0_V, .... ); ....
.... end behav;

 

As fast check you could try to change the block-level I/O protocol of function A and check the interface summary on synthesis report.

View solution in original post

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@datang
Newbie
Newbie
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Registered: ‎07-28-2017
Thank you so much. I try to change the block IO protocol of function A and I can trigger when function A starts and stops. But this have a small problem, when i change the block IO protocol of function A, latency of top module increases.
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