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Adventurer
Adventurer
1,572 Views
Registered: ‎11-06-2017

An AXI-Lite Register between PS and PL which has Write/Read access from both PS and PL!

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Dears, 

I want to define an AXI-lite Register between PS and PL with Read/Write access from both the PS and PL. What I tried is the following code: 
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#include <ap_int.h>
#include <stdint.h>

void test (ap_uint<64> InOutReg)
{
#pragma HLS INTERFACE s_axilite port=return bundle=A
#pragma HLS INTERFACE s_axilite port=InOutReg bundle=A

    ap_uint<64> temp,temp2;
    temp = InOutReg;
    temp2 = 2 * temp;
    InOutReg = temp2;
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

The problem is: when I set the "InOutReg" register from SDK to 5, I expect when I get back the register the value would be 10 but it shows 5 and remains unchanged. It seems that the line " InOutReg = temp2" is not issuing or needs some other pragma or a tricky method to overwrite this register from PL! 

What I need is a single shared address between PS and PL to be able to write and read from both side! 

I would be grateful if some one please reply. 
fkhm


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Scholar u4223374
Scholar
1,864 Views
Registered: ‎04-26-2015

Re: An AXI-Lite Register between PS and PL which has Write/Read access from both PS and PL!

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The only way I've ever found to get read-write functionality from HLS is to use a RAM instead ... which requires there to be at least two elements (I'm pretty sure you can't persuade HLS to do a 1-element RAM). It'll probably occupy a whole block RAM too as LUT RAM can't do two write ports.

 

It's annoying, and I'd really like Xilinx to fix it, but I suspect that have higher priorities at the moment.

5 Replies
Contributor
Contributor
1,545 Views
Registered: ‎03-13-2017

Re: An AXI-Lite Register between PS and PL which has Write/Read access from both PS and PL!

Jump to solution
Hello. You need to pass the OutVarible as reference with &:

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#include <ap_int.h>
#include <stdint.h>

void test (ap_uint<64>& InOutReg)
{
#pragma HLS INTERFACE s_axilite port=return bundle=A
#pragma HLS INTERFACE s_axilite port=InOutReg bundle=A

InOutReg = 2*InOutReg;
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

--------------------------------------------------------------------------------------------
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Adventurer
Adventurer
1,535 Views
Registered: ‎11-06-2017

Re: An AXI-Lite Register between PS and PL which has Write/Read access from both PS and PL!

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Hello @rosa_bpc

Thank you for your interest to my question. 

I already have tried this but the HLS diverges the Register to _i and _o version of that register. In the other word here is a snippet from the generated  *_hw.h file:

#define XXSMLL_REG_CTRLER_V01_REGISTERS_ADDR_INOUTREG_V_I_DATA 0x180
#define XXSMLL_REG_CTRLER_V01_REGISTERS_BITS_INOUTREG_V_I_DATA 16
#define XXSMLL_REG_CTRLER_V01_REGISTERS_ADDR_INOUTREG_V_O_DATA 0x188
#define XXSMLL_REG_CTRLER_V01_REGISTERS_BITS_INOUTREG_V_O_DATA 16
#define XXSMLL_REG_CTRLER_V01_REGISTERS_ADDR_INOUTREG_V_O_CTRL 0x18c

This implies that SDK should access to two different addresses in order to write/read (write to *_V_I_DATA register and check the result from *_V_O_DATA register. I was wondering if it is possible to have one shared address between PS and PL to write and read from both side. Maybe, in practice there are technical limitations (the way hardware is exploit). I don't know, maybe I am wrong and the way I am seeking for is not a correct way to take advantage of it :(.

Thanks,
fkhm

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Scholar u4223374
Scholar
1,865 Views
Registered: ‎04-26-2015

Re: An AXI-Lite Register between PS and PL which has Write/Read access from both PS and PL!

Jump to solution

The only way I've ever found to get read-write functionality from HLS is to use a RAM instead ... which requires there to be at least two elements (I'm pretty sure you can't persuade HLS to do a 1-element RAM). It'll probably occupy a whole block RAM too as LUT RAM can't do two write ports.

 

It's annoying, and I'd really like Xilinx to fix it, but I suspect that have higher priorities at the moment.

Adventurer
Adventurer
1,515 Views
Registered: ‎11-06-2017

Re: An AXI-Lite Register between PS and PL which has Write/Read access from both PS and PL!

Jump to solution

Hi @u4223374

Thank you for your analysis. 

Regards,
fkhm

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Adventurer
Adventurer
1,426 Views
Registered: ‎11-06-2017

Re: An AXI-Lite Register between PS and PL which has Write/Read access from both PS and PL!

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Hello dears: @u4223374@rosa_bpc ,

Even though this might be out of the context of this topic (HLS), I was able to implement what I exactly wanted (Write/Read access from both PS and PL) via a VHDL based Slave AXI-Lite Register implemented by Vivado IP Generator. I manipulated the generated interface in such way that was my desired. 

I am still seeking for the HLS version of this goal.

Thank you,
fkhm


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