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puv97
Adventurer
Adventurer
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Registered: ‎01-28-2021

Analysis report not generated

Hi all,

 

I'm running an HLS synthesis to obtain the latency because I'm unrolling some code. I'm using Vivado HLS 2020.1 and the HLS code is in C++. Now, if I unroll with a lower factor everything works OK, but if I unroll a big part there is the problem. The synthesis finishes correctly but the analysis is not generated, this is the Console report:

 


Starting C synthesis ...
/home/paula/Documents/Vivado2020/Vivado/2020.1/bin/vivado_hls /home/paula/Desktop/Vivado_hls/prueba_spectral_no_unroll/prueba_spectral/solution1/csynth.tcl
INFO: [HLS 200-10] Running '/home/paula/Documents/Vivado2020/Vivado/2020.1/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'paula' on host 'paula-GDEM' (Linux_x86_64 version 5.4.0-77-generic) on Mon Jul 05 11:43:20 CEST 2021
INFO: [HLS 200-10] On os Ubuntu 18.04.2 LTS
INFO: [HLS 200-10] In directory '/home/paula/Desktop/Vivado_hls/prueba_spectral_no_unroll'
Sourcing Tcl script '/home/paula/Desktop/Vivado_hls/prueba_spectral_no_unroll/prueba_spectral/solution1/csynth.tcl'
INFO: [HLS 200-10] Opening project '/home/paula/Desktop/Vivado_hls/prueba_spectral_no_unroll/prueba_spectral'.
INFO: [HLS 200-10] Adding design file 'preprocess.cpp' to the project
INFO: [HLS 200-10] Adding test bench file 'preprocess_test.cpp' to the project
INFO: [HLS 200-10] Opening solution '/home/paula/Desktop/Vivado_hls/prueba_spectral_no_unroll/prueba_spectral/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xczu9eg-ffvb1156-2-e'
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_export -vivado_optimization_level=2
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: set_clock_uncertainty default
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.25ns.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_export -vivado_optimization_level=2
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: set_clock_uncertainty default
INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [HLS 200-10] Analyzing design file 'preprocess.cpp' ...
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1729.109 ; gain = 1295.711 ; free physical = 5134 ; free virtual = 7612
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1729.109 ; gain = 1295.711 ; free physical = 5134 ; free virtual = 7612
INFO: [HLS 200-10] Starting code transformations ...
INFO: [XFORM 203-603] Inlining function 'top' into 'top_pl' (preprocess.cpp:222).
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1729.109 ; gain = 1295.711 ; free physical = 5129 ; free virtual = 7608
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1729.109 ; gain = 1295.711 ; free physical = 5126 ; free virtual = 7605
INFO: [HLS 200-489] Unrolling loop 'matrix_columns' (preprocess.cpp:165) in function 'f_spectral_correction' completely with a factor of 25.
INFO: [HLS 200-489] Unrolling loop 'imgCube_column' (preprocess.cpp:167) in function 'f_spectral_correction' completely with a factor of 405.
INFO: [XFORM 203-712] Applying dataflow to function 'top_pl', detected/extracted 3 process function(s):
'fifo_0_reader'
'f_spectral_correction'
'fifo_1_writer'.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1729.109 ; gain = 1295.711 ; free physical = 5057 ; free virtual = 7537
WARNING: [XFORM 203-631] Renaming function 'f_spectral_correction' to 'f_spectral_correctio' (preprocess.cpp:164:2)
INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:38 ; elapsed = 00:00:37 . Memory (MB): peak = 1729.109 ; gain = 1295.711 ; free physical = 5019 ; free virtual = 7493
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'top_pl' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'fifo_0_reader'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 37.26 seconds; current allocated memory: 273.359 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.01 seconds; current allocated memory: 273.436 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'f_spectral_correctio'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 555.6 seconds; current allocated memory: 376.475 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
/home/paula/Documents/Vivado2020/Vivado/2020.1/bin/loader: line 286: 24285 Killed "$RDI_PROG" "$@"
Finished C synthesis.

 

 

When I click on Analysis it says "Cannot find diagram file, please run synthesis first"

 

I don't know what to do, thanks !

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