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Visitor mvsoliveira
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Registered: ‎03-21-2017

Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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For instance, the IEEE tutorial "VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in
VHDL, Verilog and C" states the following:

"Hardware structure can be modeled equally effectively in both VHDL and Verilog."

If then, we look to HLS:

Even if the C/C++ code has to be highly customized, one can say that any circuit that can be written in VHDL/Verilog can also be described using HLS? 

 

Thanks.

 

Marcos

 

 

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Scholar u4223374
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Registered: ‎04-26-2015

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@mvsoliveira That's pretty much exactly what @dpaul24 was getting at. You can describe the same behaviour, but it may not be as fast or efficient. HLS might decide to insert registers, and there's nothing you can do about it.

 

Fundamentally, HLS is not able to produce a design that is in every way identical to an arbitrary Verilog/VHDL one. Some of this is just down to acceptable operations - HLS will not use a quad-port LUT RAM, will not schedule an AXI Master read and write simultaneously (on the same AXI Master - even though this is technically allowed by the standard), etc. Some of it is just how HLS is designed; you cannot (at least with any degree of robustness) make a HLS design that will count clock cycles. And some of it is in the category of "technically possible, but a horrible idea" - inherently parallel algorithms are an example of this, since HLS is very deliberately written to match the behaviour of a single-threaded program.

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Scholar dpaul24
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Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@mvsoliveira,

Even if the C/C++ code has to be highly customized, one can say that any circuit that can be written in VHDL/Verilog can also be described using HLS?

For synthesizable hardware, more or less yes. But that vhd/v may not be as efficient as a code written directly by an experienced logic design egnineer. At this time not, but I don't know it may be better after 5-10 years when HLS algos is supposed to be improved.

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Visitor mvsoliveira
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Registered: ‎03-21-2017

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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Thank you very much @dpaul24 for your reply. I was hoping for this response direction. 

I have written the following post in the Xilinx support but did not get a response yet: 

 

Concerning the above post, I have the equivalent code of the 5 comparison-exchange operations in a single combinational path for VHDL. I can post it if needed. However, I am not finding the way yet of doing the same in HLS. Could you please help me with that? 

 

Thanks.

 

Marcos

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Scholar u4223374
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Registered: ‎04-26-2015

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@mvsoliveira That's pretty much exactly what @dpaul24 was getting at. You can describe the same behaviour, but it may not be as fast or efficient. HLS might decide to insert registers, and there's nothing you can do about it.

 

Fundamentally, HLS is not able to produce a design that is in every way identical to an arbitrary Verilog/VHDL one. Some of this is just down to acceptable operations - HLS will not use a quad-port LUT RAM, will not schedule an AXI Master read and write simultaneously (on the same AXI Master - even though this is technically allowed by the standard), etc. Some of it is just how HLS is designed; you cannot (at least with any degree of robustness) make a HLS design that will count clock cycles. And some of it is in the category of "technically possible, but a horrible idea" - inherently parallel algorithms are an example of this, since HLS is very deliberately written to match the behaviour of a single-threaded program.

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Visitor mvsoliveira
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Registered: ‎03-21-2017

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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Hi @u4223374  and @dpaul24,

Thank you very much for your reply. You have clarified very well my question. I am very grateful you had a look at it. 

The research we are doing is part of my Ph.D. Thesis, and it would be nice that I have references on the HLS limitations. 

Do you know any scientific publication or Xilinx documentation that backs up some of the following sentences written by you? 

1) HLS is not able to produce a design that is in every way identical to an arbitrary Verilog/VHDL one

2) HLS is very deliberately written to match the behavior of a single-threaded program

3) You cannot (at least with any degree of robustness) make an HLS design that will count clock cycles

Again, very thank you in advance for the enormous help.

Cheers.

Marcos

 

 

 

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Scholar richardhead
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Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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May I add a cynical point here.

Xilinx is a chip manufacturer, and it's job is to sell chips. HLS (or other attempts) have been around for quite a long time, but never really could outperform HDL, and because the market was smaller, and chips were small, firmware engineers could get chips produced at a decent speed.

As chips get bigger, designs get more complex and firmware designs get longer to bring to market. HLS comes into its own as you can spin up designs faster. Also, because it takes in C, Xilinx sell it that any software engineer can do it, and hence you suddenly increase your market potential as you can sell to software teams. designs produced quickly tend to be big and inefficient, so you need a bigger chip to put it in, and hence a nice expensive chip sold by xilinx. (you could also maybe argue that theres little incentive for Xilinx to improve efficiency because of this, but it will depend on if theres a sale in it for them).

HLS uses xilinx IP and AXI interconnects. Basically, you're boxed into a controlled environment. I doubt you could write a MIG or MAC in HLS. In the same way C will still need some custom assembly, HLS will still need some HDL.

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Scholar dpaul24
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Registered: ‎08-07-2014

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@mvsoliveira,

The research we are doing is part of my Ph.D.

@richardheadputs it correctly above.......You can have an Ethernet MAC coded in HDL and also in HLS and then compare their efficiencies.

You need to read more research papers on the advantages and limitations of HLS.

One example is here - https://www.researchgate.net/publication/301370457_The_advantages_and_limitations_of_high_level_synthesis_for_FPGA_based_image_processing

There could be many such publications and you can draw info from them.

 

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Observer ivank33
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Registered: ‎07-06-2018

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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Interesting discussion. My 2 cents:

There's 40+ years of academic research on HLS (aka Behavioral Synthesis). Just on example: "A Survey of High-Level Synthesis Systems" edited in 1991 covers 40 HLS tools.

VHDL/Verilog describe hardware. Parallelism is inherent. Describing sequential behavior is done by explicitly writing state machines or another kind of sequencer. However, since these languages are low-level down to the gate level and clock cycle, you can describe any kind of architecture in a (probably) optimal way. This means that you can get the best performance/lowest area on a specific FPGA architecture.

C/C++ describe operations executed on a processing unit. Sequencing is inherent. Parallelism is not natural. HLS tools schedule and map a list of operations (C code) on predetermined architectures. The C code has to match specific coding patterns for the compiler to map it on an efficient architecture (e.g. dataflow). HLS is limited in the type or architectures it can implement.

So I would agree that "HLS is not able to produce a design that is in every way identical to an arbitrary Verilog/VHDL one".

Ivan

 

 

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@mvsoliveira Unfortunately I don't have any specific documentation for this; it's more that there isn't specific documentation to the contrary.

 

(1) Is an inherent property of higher-level languages. If you go from assembly to C/C++ on a CPU, you're already losing a lot of the ability to do cycle-accurate timing (although in some cases it's still possible) in exchange for making many tasks easier. If you go from C/C++ to Python, Java, or MATLAB, you lose the ability to manage memory yourself, in exchange for not having to manage memory yourself. HLS is no different in this regard; you lose the ability to control many of the low-level aspects, but in exchange you no longer need to control those aspects.

(2) You really just need to look at UG902 and search for "thread". HLS does support some threading, but only in SystemC. There is not a single mention of threading elsewhere.

(3) Basically comes down to reading UG902. To count clock cycles reliably you would need a pragma that says "this must take exactly one cycle per loop, it must have no input delay for the trigger signals, and the counter can't be optimized-away". There is no pragma for any of these. You can pipeline the loop at II=1, but that just means that it completes one iteration per cycle - not that each iteration takes one cycle. I suspect that you might be able to do something close with the LATENCY pragma and volatile variables, but I doubt it'd be consistent - if you wind up the clock speed then HLS will quietly insert a couple of extra clock cycles, or if you go to a different version it'll decide that it can do an optimization that breaks the design completely.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-04-2017

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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As others mentioned, not everything can be done using HLS. In HDL you have a finer control on where to insert a register, parallelizing operations etc. Using HLS, the tool is converting a sequentially executing C/C++ code to an equivalent HDL by scheduling the operations. If we were to do similar to HDL, it would need extra constraints which needs to be implemented by HLS, and that i believe would more or less be a kind of loosing the abstraction 

Thanks,

Nithin

Scholar u4223374
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Registered: ‎04-26-2015

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@nithink brings up a very good point. If you included enough pragmas in HLS to make it perfectly match HDL code, then you would effectively be writing HDL code - but doing so in an extremely awkward way. To use this you'd have to know exactly what behaviour you were aiming for (to the point that it'd be easy to code it in HDL) so it'd make much more sense to just write the whole thing in HDL rather than trying to bludgeon HLS into doing it.

 

I think that one very useful feature that Xilinx should look into is inline HDL in HLS (equivalent to inline assembly in C). This would help with the above situation, where you might have a big, complex project but in one specific area you want to show HLS exactly how to implement it. Currently the only option is to use an AXI Master to talk to separate AXI hardware, which (a) makes it impossible to simulate, and (b) adds substantial resources and latency.

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Visitor mvsoliveira
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Registered: ‎03-21-2017

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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Thanks a lot @dpaul24@u4223374@richardhead@ivank33@nithink for all the comments. 

I would stick with a slightly adapted answer from @u4223374

Fundamentally, HLS is not able to produce a design that is in every way identical to an arbitrary Verilog/VHDL one.
HLS might decide, for instance, to insert registers, and in some cases, there's nothing you can do about it.

Concerning the documentation, I agree with: it's more that there isn't specific documentation to the contrary.

FYI, the specific example I posted here, @nithink has proposed a solution in which the register can be prevented from being implemented. I believe that in some cases, one may find a way of controlling if registers are implemented or not. But the same might not be true for all the cases. 

To conclude, I understand that HLS is not the recommended design flow when cycle-accurate timing is needed. And in addition to not being recommended, in some cases, it may be impossible to describe a design that is in every way identical to an arbitrary Verilog/VHDL one.

I would agree with @u4223374, that would be interesting if Xilinx could look into inlining HDL in HLS, similarly with what can be done inlining assembly in C. 

Thanks all of you very much !!!

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-04-2017

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@mvsoliveira @u4223374  Currently HLS supports RTL black box flow, where a user can plug in their RTL in their design. 

 

Thanks,

Nithin

Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@nithink Ooh, that's what I get for sticking with 2016.2. Time to upgrade, I think.

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Registered: ‎04-15-2019

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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There is a way to use a high level language to do anything HDLs can do, RapidWright. In fact RapidWright.io can do things HDLs can't do.

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Explorer
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Registered: ‎07-18-2011

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@nithink 

Does 2018.3.1 support black-box RTL, or just the later 2019 versions?

Is there documentation/examples on how to insert RTL into HLS?

This sounds like a great feature, exactly what I need!

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-04-2017

Re: Any circuit that can be described in VHDL/Verilog can be also described using HLS?

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@reaiken  This is avaialble in 2019.x version. To give a brief summary of how it works, let's say we have a design in which there is a sub function for which you already have RTL, then that function can be made as black box and during the RTL packaging, HLS will pick the RTL. The interface info, etc can be specified using json file

Thanks,

Nithin

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