10-31-2020 03:27 AM
I have a image AI accelerator project required big bus width of AXI-Stream protocol. I have tried many versions of VIVADO HLS version from 2016.2/2016.4... to 2018.4, but they are all compiled failed by big AXI-stream bus width ? I also try to change the HLS source code to extend the bus width, but it also failed at last.
General image AI accelerator will input 3 channels 24bits (each channel 8bits), after some convolution layers, it will be up to 1024 channels (1024x8 bits). If Vivado HLS could support big bus width, I think that AI accelerator could easy be carried out.
10-31-2020 04:32 AM
If I got your question right, you want a bus for 1024x8 bits, so 8192 bits, right? As far as I know, AXI4 buses go to 1024 bits, so, it looks like you are asking for too much
10-31-2020 12:52 PM - edited 10-31-2020 12:53 PM
There is no limitation in the AXI spec, TDATA can be any width dividisible by 8.
There may be limits on widths in the Xilinx IP. But 8192 bits wide is VERY wide. The widest bus I have seen considered would be 512 bits for a 100Gbs Mac. Why do you need 8192 bit interface? Why cant the channels be interleaved through time?
10-31-2020 01:31 PM
@richardhead , you talk about the spec and you are right. Then, unless writing all AXI-related in HDL, when it comes to the available blocks (interconnects, DMA, etc.) limitations come up. For example, the AXI interconnect:
Interface data widths: