cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mattiasu96
Observer
Observer
216 Views
Registered: ‎09-16-2020

Axi stream synthesized size

Jump to solution

I am writing an IP which works with an input stream and an output stream with the following data types: 

#define INTEGER_PART 4
#define BITS_NUMBER 20
#define SECONDS 2
#define SAMPLE_RATE 44100


#include <stdio.h>
#include <ap_fixed.h>
#include <hls_stream.h>

typedef ap_fixed<BITS_NUMBER, INTEGER_PART> InputType;

typedef struct {
		InputType coeffs_b0;
		InputType coeffs_b1;
		InputType coeffs_b2;
		InputType coeffs_a1;
		InputType coeffs_a2;
		InputType data_in;

	}input_struct;

template<class DT, int D, int U, int TI, int TD>
	struct MyApAxis{
		DT data;
		ap_uint<(D+7)/8> keep;
		ap_uint<(D+7)/8> strb;
		ap_uint<U> user;
		ap_uint<1> last;
		ap_uint<TI> id;
		ap_uint<TD> dest;
	};


typedef MyApAxis<input_struct, 32 ,1,1,1> InputStreamType;
typedef hls::stream<InputStreamType> InputStream;

typedef MyApAxis<InputType,32,1,1,1> OutputStreamType;
typedef hls::stream<OutputStreamType> OutputStream;

void iir_hls (
		InputStream &input_stream,
		OutputStream &output_stream
){
#pragma HLS interface axis register both port=input_stream
#pragma HLS interface axis register both port=output_stream
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS DATAFLOW

........ my ip function .......

};

 

When I export my IP to Vivado I get the following axi stream sizes:

iir_ip.png

Where the input stream has size of 256 bits. Where does this size come frome? 

according to my calculations, I have an input data structure of 20*6 = 120 bits, plus the control signals (last, ID ecc....) which are 32+1+1+1 = 35, so in total my input should be 155 bits.

The same holds for the output stream, I expected 55 bits instead of 96.

Why am I getting these numbers in Vivado? Are my calculation right or am I missing something? 

0 Kudos
1 Solution

Accepted Solutions
p27803
Contributor
Contributor
164 Views
Registered: ‎03-31-2017

Please read the Vitis / HLS documentation on structures, aggregation, disaggregation, alignment, padding of values to a power of 2, etc.  I believe once you understand this, you will see how your stream widths are determined.

View solution in original post

0 Kudos
2 Replies
p27803
Contributor
Contributor
165 Views
Registered: ‎03-31-2017

Please read the Vitis / HLS documentation on structures, aggregation, disaggregation, alignment, padding of values to a power of 2, etc.  I believe once you understand this, you will see how your stream widths are determined.

View solution in original post

0 Kudos
mattiasu96
Observer
Observer
121 Views
Registered: ‎09-16-2020

Is it this one? https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf 

At page 151 and on it says the the element of a structure are aligned on a 4-byte boundary. However I am using a struct inside a struct, and I do not know how it behaves in this situation.

I tried some calculations, but I am not able to get results coherent with the sizes I get in the implemented design in Vivado. 

0 Kudos