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alexmontgomerie
Participant
Participant
863 Views
Registered: ‎05-14-2018

BRAM usage large for FIFO

I have noticed that when instantiating a BRAM FIFO, the BRAM usage can be a lot larger than expected. In the below synthesis report, we can see that although the size suggests the need for 5 BRAM18k, it is instead using 8. Is there something I'm missing? And is there any way to get the resources down to a more reasonable amount?

Thanks, 

Alex

    * FIFO: 
    +----------------------------+---------+----+----+-----+------+-----+---------+
    |            Name            | BRAM_18K| FF | LUT| URAM| Depth| Bits| Size:D*B|
    +----------------------------+---------+----+----+-----+------+-----+---------+
    |line_buffer_0_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|
    |line_buffer_1_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|
    |line_buffer_2_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|
    |line_buffer_3_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|
    |line_buffer_4_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|
    |line_buffer_5_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|
    |line_buffer_6_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|
    |line_buffer_7_V_V_fifo_U    |        8|  92|   0|    -|  5491|   16|    87856|

 

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rsarkari
Xilinx Employee
Xilinx Employee
810 Views
Registered: ‎06-20-2018

Hi @alexmontgomerie ,

Could you please share more details as which report is this? Vivado Synthesis or C Synthesis. 

Also, could you please share the code snippet using this buffer or the Vivado synthesis detailed utilization report for this module?

Regards,
Rajat
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alexmontgomerie
Participant
Participant
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Registered: ‎05-14-2018

Hi Rajat,

Thanks for getting back to me. This is a C Synthesis report. The HLS code is as follows: 

    hls::stream<ap_fixed<16,8,AP_RND,AP_SAT>> line_buffer[8];
    #pragma HLS STREAM variable=line_buffer depth=5491
    #pragma HLS ARRAY_PARTITION variable=line_buffer complete dim=0
    #pragma HLS resource variable=line_buffer core=FIFO_BRAM

 from my understanding, this should consume 5 BRAM for each fifo, as 5491*16/18000 rounds to 5. 

Best,

Alex

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rsarkari
Xilinx Employee
Xilinx Employee
721 Views
Registered: ‎06-20-2018

Hi @alexmontgomerie ,

An 18 Kb block RAM can be configured with independent port widths for each of those ports as 16K x 1, 8K x 2, 4K x 4, 2K x 9 or 1K x 18 (when used as TDP memory). If only one write and one read port are used, an 18 Kb block RAM can additionally be configured with a port width of 512 x 36 bits (when used as SDP memory). Kindly refer the below documentation:

https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf 

Based on the above info, 16*1 BRAMs will be inferred.

5491/1024 = 5.4 ~ 6 BRAMS

1 decoder logic; totaling to 7 BRAMs. Could you please run VIVADO Synthesis and share the resource numbers for this streaming FIFO along with the platform name?

Regards,
Rajat
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rsarkari
Xilinx Employee
Xilinx Employee
613 Views
Registered: ‎06-20-2018

With Vitis 2020.2 released, the above calculations are proved and the results can be seen below.

rsarkari_0-1622114467413.png

Regards,
Rajat
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frederic
Xilinx Employee
Xilinx Employee
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Registered: ‎04-14-2013

Vivado RTL synthesis ultimately decides how to tech map these RTL RAMs of 5491x16-bit.

It looks at the address and sees it can be directly covered by 8k which leaves you with 4-bit of data and since you need 16-bit you get 4 of these BRAMs...

By default it won't give you the 2k by 16-bit in 3 BRAMs as it won't be as good for performance and logic utilization.

alexmontgomerie
Participant
Participant
543 Views
Registered: ‎05-14-2018

Hi both, 

Thank you for getting back to me. The resource report given in my first post was done for Vivado HLS 2019.1, I tried for 2020.1 also, but got the same results. I have attached the FIFO that Vivado HLS generates. I also suspected that it chose the BRAM based on the fact that it requires an 8K address bus, even if all of that space isn't used.

Is there a model available of the BRAM usage for Vivado HLS that tells us what it is basing it's estimates on?

Thanks,

Alex

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