cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor
Visitor
270 Views
Registered: ‎05-20-2014

[BUG] ap_fifo interface broken for System Generator RTL Export

Hello,

when I export my projects using 2019.2 for use in System Generator in- and outputs that use the interface ap_fifo expect the data type "illegal" in Simulink/System Generator. Simulation fails for this reason. It also doesn't matter whether the C++ function argument is a pointer or hls::stream.

Everything works correctly and as expected using HLS 2018.3.

My system: Windows 10 64 Bit, Matlab R2019b, Vivado 2019.2

See the two attached images for the table of the HLS interface overview and the mask of the Vivado HLS System Generator block.

For 2018.3 the input text reads "values_V_dout:Fix_16_15".

interface.png
sysgen.png
0 Kudos
1 Reply
Highlighted
Visitor
Visitor
199 Views
Registered: ‎05-20-2014

Re: [BUG] ap_fifo interface broken for System Generator RTL Export

I found the reason. If the input or output port is defined as ap_fifo and the compilation target is the System Generator HLS 2019.1 and 2019.2 will produce an erroneous auxiliary.xml in <project>/<solution_name>/impl/sysgen.

The type will always be "bool" and the fractionWidth will always be "0". Changing these false entries by hand will remove all problems.

Please fix this behavior for the next release.

auxiliary.PNG
0 Kudos