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linzhongduo
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Registered: ‎10-09-2014

Best practice of axi streaming interface with non-blocking read/write

Hi,

I have been using HLS a lot in high throughput and low latency designs. For my applications, the non-blocking read/write is necessary, eg. multiplexing two input to one output whenever any of input channels has data. The code will look like:

void mux(stream<int>& in0, stream<int>& in1, stream<int>& out)

{

    if (!in0.empty()) out.write(in0.read());

    else if (!in1.empty()) out.write(in1.read());

Since axi stream interface is used extensively in Xilinx cores, we have made all the interfaces axis. However I notice that from the ug902 (2019 version page 221), it states that non-blocking is not supported in axis interface. So how can I design a core like this? There are always several problems bugging me with axis interface and I do hope there is a good solution for each:

1. If I don't use register option, I will need register slice between two hls IP cores.

2. If I use register option, it actually affects the latency of the logic. So if I have a function with lots of logic I want to apply LATENCY pragma, just because the function is writing to external port, the latency needs to be increased by one.  I think the old "resource axi4stream" approach is quite perfect as it is simply adding an adapter to the core. 

I do think the best strategy is to use the adapter approach like the old "resource axi4stream" pragma, and adds support of depth so that when users specify a depth, it will generate a fifo instead of a register slice. This will 1) avoid the effect on latency pragma per function, 2) avoid register slice and 3) easily have input fifo.

Thanks,

Jimmy

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9 Replies
aoifem
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Registered: ‎11-21-2018

Hi @linzhongduo 

 

Thanks for your question! 

Just to let you kow, the information in UG902 is out of date and support for non-blocking read/write is possible. This has already been flagged with development and they are working on fixing the information in a future release. 

Sorry for the inconvenience! 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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linzhongduo
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Registered: ‎10-09-2014

Hi @aoifem ,

Thanks for confirming this. Any suggestions or plan to support that "register pragma does not affect latency" and "easily generate fifo in interface"?

Thanks again,

Jimmy

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nmoeller
Xilinx Employee
Xilinx Employee
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Registered: ‎09-05-2018

Hey @linzhongduo ,

You can use the STREAM directive to set the depth of the FIFO greater than the default of 1. I'm not sure I understand the other half of your quesiton.

Nicholas Moellers

Xilinx Worldwide Technical Support
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linzhongduo
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Registered: ‎10-09-2014

Hi @nmoeller ,

Thanks for prompt repsonse. You can see my question statement for the details. Basically I want to set the depth in the interface not internal fifo, and as far as I know, the STREAM pragma only works with internal one. The fifo can also serve as register slice so that I don't have to instantiate one outside. For the latency, image I have a simply function like the following, I can use latency pragma to set it to be 0, but when "out" is connected to top level output port with axis register mode, the latency will have to be 1. It causes trouble to me when I use the same function multiple times. Also, note that the axi sregister mode cannot check full signal of the output, this is different from the old "resource AXI4STREAM" pragma.

void move(stream<int>& in, stream<out>& out) 

{

if (!in.empty()) out.write(in.read());

}

Thanks,

Jimmy

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nmoeller
Xilinx Employee
Xilinx Employee
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Registered: ‎09-05-2018

Hey @linzhongduo ,

I agree that you're stuck with an internal FIFO, I'm not aware of any other way to do that in HLS.

I was going to suggest setting the INTERFACE directive register_mode argument to 'off' until you mentioned it. But I don't understand why it the stream can't check the full signal if this is set, the hls::stream class has the function. Does something like the following not work?

void move(stream<int>& in, stream<out>& out) {
#pragma HLS INTERFACE axis off latency=0 port=in
#pragma HLS INTERFACE axis off latency=0 port=out
  if ( !in.empty() && !out.full() ) out.write(in.read());
}
Nicholas Moellers

Xilinx Worldwide Technical Support
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linzhongduo
Explorer
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Registered: ‎10-09-2014

Hi @nmoeller ,

That will work, but you cannot check full signal and at the same time have register pragma on. So if you decide to check full signal on output port, you will have to remember to manually add a register slice when connecting to other hls IPs. So the following will not work (it will simply ignore the register pragma). The old pragma works without any problem though.

void move(stream<int>& in, stream<out>& out) {
#pragma HLS INTERFACE axis register both port=in
#pragma HLS INTERFACE axis register both port=out
  if ( !in.empty() && !out.full() ) out.write(in.read());
}

Thanks,

Jimmy

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marek.kvas
Observer
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Registered: ‎02-16-2017

Dear aoifem,

UG902 still says non-blocking access is not possible for AXI streams. It is ten months (and two releases) after your message about preparations to fix documentation. Is it still being fixed, or functionality will be adjusted to the documentation?

Thanks for update

Marek

aoifem
Moderator
Moderator
903 Views
Registered: ‎11-21-2018

Hi @marek.kvas 

 

Thanks for bringing this to my attention. It seems the person who initially flagged this issue isn't working on this team anymore, so I think the issue has been overlooked. I've contacted the Documentation team directly about this, and I will try to push this issue as I agree it's been open for a long time now. 

Sorry for the inconvenience. 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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marek.kvas
Observer
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Registered: ‎02-16-2017

Thanks @aoifem ,

I am glad to hear, it is still true that the bug is in the documentation, not functionality.

Marek

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