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jtani
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Registered: ‎06-21-2011

Bidirectional pin problem with HLS

Hi @ all,

I try to implement a bidirectional port in HLS.

In VHDL I would write this:

			WIZ5300_DATEN_I			:in std_logic_vector(15 downto 0);
			WIZ5300_DATEN_O			:out std_logic_vector(15 downto 0);
			WIZ5300_DATEN_T			:out std_logic;

With WIZ5300_DATEN_T I can set the TRI-STATE-Value.

And with WIZ5300_DATEN_O and WIZ5300_DATEN_I I can access the data (depending on the setting of WIZ5300_DATEN_T).

 

But now I have to do this in HLS (I am using VIVADO 2015.4).

I did not find a special port mode for bidirectional ports.

I already wrote a few HLS-IPs. But all of them contain only simple inputs and/or outputs.

This is the first time, I need a bidirectional port.

 

This is, what I tried: 

void jt_wiz5300(
		ap_uint<1> _befehl_reset,
		ap_uint<16> _pin_WIZ5300_DATEN_i,
		ap_uint<16> *_pin_WIZ5300_DATEN_o,
		ap_uint<16> *_pin_WIZ5300_DATEN_t
		) {
	#pragma HLS INTERFACE s_axilite port=return bundle=BUS_A
	#pragma HLS INTERFACE s_axilite port=_befehl_reset bundle=BUS_A

	#pragma HLS INTERFACE ap_none register port=_pin_WIZ5300_DATEN_i
	#pragma HLS INTERFACE ap_none register port=_pin_WIZ5300_DATEN_o
	#pragma HLS INTERFACE ap_none register port=_pin_WIZ5300_DATEN_t

	if(_befehl_reset) {
		*_pin_WIZ5300_DATEN_o = 0;
		*_pin_WIZ5300_DATEN_t = 0x0000;
	} else {
		*_pin_WIZ5300_DATEN_o = 100;
		*_pin_WIZ5300_DATEN_t = 0xFFFF;
	}
}

 

But then I get three ports instead of one.

In the generated VHDL code a "_V" were appended.

(I already tried _pin_WIZ5300_DATEN_t with 1 bit length and with 16 bit length)

entity jt_wiz5300 is
generic (
    C_S_AXI_BUS_A_ADDR_WIDTH : INTEGER := 5;
    C_S_AXI_BUS_A_DATA_WIDTH : INTEGER := 32 );
port (
    ap_clk : IN STD_LOGIC;
    ap_rst_n : IN STD_LOGIC;
    p_pin_WIZ5300_DATEN_i_V : IN STD_LOGIC_VECTOR (15 downto 0);
    p_pin_WIZ5300_DATEN_o_V : OUT STD_LOGIC_VECTOR (15 downto 0);
    p_pin_WIZ5300_DATEN_t_V : OUT STD_LOGIC_VECTOR (15 downto 0);
    s_axi_BUS_A_AWVALID : IN STD_LOGIC;
    s_axi_BUS_A_AWREADY : OUT STD_LOGIC;
    s_axi_BUS_A_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_BUS_A_ADDR_WIDTH-1 downto 0);
    s_axi_BUS_A_WVALID : IN STD_LOGIC;
    s_axi_BUS_A_WREADY : OUT STD_LOGIC;
    s_axi_BUS_A_WDATA &colon; IN STD_LOGIC_VECTOR (C_S_AXI_BUS_A_DATA_WIDTH-1 downto 0);
    s_axi_BUS_A_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_BUS_A_DATA_WIDTH/8-1 downto 0);
    s_axi_BUS_A_ARVALID : IN STD_LOGIC;
    s_axi_BUS_A_ARREADY : OUT STD_LOGIC;
    s_axi_BUS_A_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_BUS_A_ADDR_WIDTH-1 downto 0);
    s_axi_BUS_A_RVALID : OUT STD_LOGIC;
    s_axi_BUS_A_RREADY : IN STD_LOGIC;
    s_axi_BUS_A_RDATA &colon; OUT STD_LOGIC_VECTOR (C_S_AXI_BUS_A_DATA_WIDTH-1 downto 0);
    s_axi_BUS_A_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
    s_axi_BUS_A_BVALID : OUT STD_LOGIC;
    s_axi_BUS_A_BREADY : IN STD_LOGIC;
    s_axi_BUS_A_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
    interrupt : OUT STD_LOGIC );
end;

 

QUESTION:

How can I implement a Tri-State-Port in HLS (not in SystemC).

I hope this is with ap_uint<16> ports possible.

 

 

 

Kindly Regards,

 

Andreas

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