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Adventurer
Adventurer
730 Views
Registered: ‎03-13-2015

Bitwise and of ap_uint limitation

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I run into problem when do logic bitwise and on wide integers. They only seem to work up to 64 bits.

const int z=70;
for(int i=60;i<z;i++)
{
	ap_uint<z> x=1;
	ap_uint<z> t1=x<<i;
	ap_uint<z> t2=x<<i;
	bool r=t2.And(t1);

cout << "ap_uint shift " << i << " bits left, (" << t1.toStringUnsigned(16) << ") bitwise AND (" << t2.toStringUnsigned(16) << ")=" << r << endl; }

This outputs:

 

ap_uint shift 60 bits left, (0x01000000000000000) bitwise AND (0x01000000000000000)=1
ap_uint shift 61 bits left, (0x02000000000000000) bitwise AND (0x02000000000000000)=1
ap_uint shift 62 bits left, (0x04000000000000000) bitwise AND (0x04000000000000000)=1
ap_uint shift 63 bits left, (0x08000000000000000) bitwise AND (0x08000000000000000)=1
ap_uint shift 64 bits left, (0x010000000000000000) bitwise AND (0x010000000000000000)=0
ap_uint shift 65 bits left, (0x020000000000000000) bitwise AND (0x020000000000000000)=0
ap_uint shift 66 bits left, (0x040000000000000000) bitwise AND (0x040000000000000000)=0
ap_uint shift 67 bits left, (0x080000000000000000) bitwise AND (0x080000000000000000)=0
ap_uint shift 68 bits left, (0x100000000000000000) bitwise AND (0x100000000000000000)=0
ap_uint shift 69 bits left, (0x200000000000000000) bitwise AND (0x200000000000000000)=0

 

Now, there is no reason for this to happen..

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Xilinx Employee
Xilinx Employee
660 Views
Registered: ‎09-05-2018

Re: Bitwise and of ap_uint limitation

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@cyviz,

The line, bool r = t2.And(t1);, is an implicit conversion from a wide (>64bits) ap_[u]int  to a builtin C/C++ integer types (ap_uint<70> to bool), which is not supported by HLS. The following code works as you expect:

 

const int z=70;
for(int i=60;i<z;i++)
{
 ap_uint<z> x=1;
 ap_uint<z> t1=x<<i;
 ap_uint<z> t2=x<<i;
 ap_uint<z> res =t2.And(t1);
 bool r = res.to_bool();
 cout << "ap_uint shift " << i << " bits left, (" << t1.toStringUnsigned(16) << ") bitwise AND (" << t2.toStringUnsigned(16) << ")=" << r << endl;
}

And the output:

 

ap_uint shift 60 bits left, (0x01000000000000000) bitwise AND (0x01000000000000000)=1
ap_uint shift 61 bits left, (0x02000000000000000) bitwise AND (0x02000000000000000)=1
ap_uint shift 62 bits left, (0x04000000000000000) bitwise AND (0x04000000000000000)=1
ap_uint shift 63 bits left, (0x08000000000000000) bitwise AND (0x08000000000000000)=1
ap_uint shift 64 bits left, (0x010000000000000000) bitwise AND (0x010000000000000000)=1
ap_uint shift 65 bits left, (0x020000000000000000) bitwise AND (0x020000000000000000)=1
ap_uint shift 66 bits left, (0x040000000000000000) bitwise AND (0x040000000000000000)=1
ap_uint shift 67 bits left, (0x080000000000000000) bitwise AND (0x080000000000000000)=1
ap_uint shift 68 bits left, (0x100000000000000000) bitwise AND (0x100000000000000000)=1
ap_uint shift 69 bits left, (0x200000000000000000) bitwise AND (0x200000000000000000)=1

More information is available on page 628 of UG902.

Nicholas Moellers

Xilinx Worldwide Technical Support
2 Replies
Scholar u4223374
Scholar
704 Views
Registered: ‎04-26-2015

Re: Bitwise and of ap_uint limitation

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Try replacing your shifts with direct assignment of different bits (eg. using the range() function). I've got  feeling that C does some odd things with the shifts (it's been a while since I tried that), possibly related to your second argument being a C integer rather than one of the ap_int types.

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Xilinx Employee
Xilinx Employee
661 Views
Registered: ‎09-05-2018

Re: Bitwise and of ap_uint limitation

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@cyviz,

The line, bool r = t2.And(t1);, is an implicit conversion from a wide (>64bits) ap_[u]int  to a builtin C/C++ integer types (ap_uint<70> to bool), which is not supported by HLS. The following code works as you expect:

 

const int z=70;
for(int i=60;i<z;i++)
{
 ap_uint<z> x=1;
 ap_uint<z> t1=x<<i;
 ap_uint<z> t2=x<<i;
 ap_uint<z> res =t2.And(t1);
 bool r = res.to_bool();
 cout << "ap_uint shift " << i << " bits left, (" << t1.toStringUnsigned(16) << ") bitwise AND (" << t2.toStringUnsigned(16) << ")=" << r << endl;
}

And the output:

 

ap_uint shift 60 bits left, (0x01000000000000000) bitwise AND (0x01000000000000000)=1
ap_uint shift 61 bits left, (0x02000000000000000) bitwise AND (0x02000000000000000)=1
ap_uint shift 62 bits left, (0x04000000000000000) bitwise AND (0x04000000000000000)=1
ap_uint shift 63 bits left, (0x08000000000000000) bitwise AND (0x08000000000000000)=1
ap_uint shift 64 bits left, (0x010000000000000000) bitwise AND (0x010000000000000000)=1
ap_uint shift 65 bits left, (0x020000000000000000) bitwise AND (0x020000000000000000)=1
ap_uint shift 66 bits left, (0x040000000000000000) bitwise AND (0x040000000000000000)=1
ap_uint shift 67 bits left, (0x080000000000000000) bitwise AND (0x080000000000000000)=1
ap_uint shift 68 bits left, (0x100000000000000000) bitwise AND (0x100000000000000000)=1
ap_uint shift 69 bits left, (0x200000000000000000) bitwise AND (0x200000000000000000)=1

More information is available on page 628 of UG902.

Nicholas Moellers

Xilinx Worldwide Technical Support