Bug Report: pragma Interface with name parameter has no effect on hls::stream interfaces

[jehandad]

Hi,

I have a couple of hls modules which are using the hls::stream for some ports. If I use the name parameter in an HLS INTERFACE pragma it has no effect on the generated verilog which still has autogenerated names ( port names followed by one '_V' or two '_V's )

I hope some one can fix this.

Thanks

[debrajr]

I quickly tried that in 2016.3 HLS and could see the name maintained in the port name as set in INTERFACE pragma for a hls::stream.

[jehandad]

Hi Debraj,

Is the "_V" in the port name expected behavior ? If not then I have attached a project that I created with Vivado HLS 2016.3 showing the "_V" appearing in the port names despite the directive. The project is an example project from the the HLS samples.  Any help would be much appreciated.

Thanks

[jehandad]

The problem persists in version 2016.4 of the software.

[ywu]

Please open a support request (SR) with Xilinx Technical Support with your test case. They will confirm and file bug report to the engineering team.