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jehandad
Participant
Participant
4,572 Views
Registered: ‎06-08-2016

Bug Report: pragma Interface with name parameter has no effect on hls::stream interfaces

Hi,

 

I have a couple of hls modules which are using the hls::stream for some ports. If I use the name parameter in an HLS INTERFACE pragma it has no effect on the generated verilog which still has autogenerated names ( port names followed by one '_V' or two '_V's )

 

I hope some one can fix this.

 

Thanks

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4 Replies
debrajr
Moderator
Moderator
4,561 Views
Registered: ‎04-17-2011

I quickly tried that in 2016.3 HLS and could see the name maintained in the port name as set in INTERFACE pragma for a hls::stream.
Regards,
Debraj
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jehandad
Participant
Participant
4,526 Views
Registered: ‎06-08-2016

Hi Debraj,

 

Is the "_V" in the port name expected behavior ? If not then I have attached a project that I created with Vivado HLS 2016.3 showing the "_V" appearing in the port names despite the directive. The project is an example project from the the HLS samples.  Any help would be much appreciated.

 

Thanks

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jehandad
Participant
Participant
4,438 Views
Registered: ‎06-08-2016

The problem persists in version 2016.4 of the software.

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ywu
Xilinx Employee
Xilinx Employee
4,414 Views
Registered: ‎11-28-2007

Please open a support request (SR) with Xilinx Technical Support with your test case. They will confirm and file bug report to the engineering team.
Cheers,
Jim