12-18-2016 05:45 AM
I have a couple of hls modules which are using the hls::stream for some ports. If I use the name parameter in an HLS INTERFACE pragma it has no effect on the generated verilog which still has autogenerated names ( port names followed by one '_V' or two '_V's )
I hope some one can fix this.
12-18-2016 06:51 AM
12-18-2016 01:51 PM
Is the "_V" in the port name expected behavior ? If not then I have attached a project that I created with Vivado HLS 2016.3 showing the "_V" appearing in the port names despite the directive. The project is an example project from the the HLS samples. Any help would be much appreciated.
12-24-2016 01:22 AM
The problem persists in version 2016.4 of the software.
12-24-2016 08:00 AM