cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mreisinger
Visitor
Visitor
234 Views
Registered: ‎11-12-2018

Bug: Vitis-HLS 2020.2: RAM_1P-Interface not possible when disaggregating a input-struct

The goal is to read sequentially from a BRAM within two cycles (II=2) from a single port. If the config-struct is packed (by default with Vitis-HLS), this works fine. However, if you split the struct with Disaggregate-Pragma, a dual-port interface is generated. This means that the BRAM is now read in parallel in the same cycle instead of sequentially with one port as desired.

Remove #pragma HLS DISAGGREGATE to see the difference. In the attachment the source code with build script is linked. I am using Vitis 2020.2.

 

#include <ap_int.h>
#include <hls_stream.h>

typedef struct {
   bool selectInput;
   ap_uint<7> in0;
   ap_uint<7> in1;
} config_t;

void bram_test(
      hls::stream<ap_uint<7>>     & inputStream,
      hls::stream<ap_uint<16>>    & outputStream,
      const config_t              & config,
      const ap_uint<16> bram [256] )
{
#pragma HLS INTERFACE AP_FIFO port=inputStream
#pragma HLS INTERFACE AP_FIFO port=outputStream
#pragma HLS INTERFACE AP_NONE port=config
#pragma HLS INTERFACE BRAM storage_type=RAM_1P latency=1 port=bram
#pragma HLS INTERFACE AP_CTRL_NONE port=return

   // BRAM-Interface according to implementation of config-struct:
   //    *) packed struct           => Single-Port-Interface (PORTA) (sequential reads)
   //    *) disaggregated struct    => Dual-Port-Interface (PORTA & PORTB) (parallel reads)
//###########################################################################################################
#pragma HLS DISAGGREGATE variable=config   // <------- comment this line to see the difference !!!!!!!!!!!!
//###########################################################################################################

   // two reads, therefore an II=2 is possible with Single-Port
#pragma HLS PIPELINE II=2

   ap_uint<7> input;
   if(inputStream.read_nb(input)) {
      ap_uint<7> cfgValue = config.selectInput ? config.in1 : config.in0;
      ap_uint<8> index = input + cfgValue;
      ap_uint<16> val0 = bram[index];
      ap_uint<16> val1 = bram[index+1];
      ap_uint<16> output = val0/2 + val1/2;
      outputStream.write(output);
   }
}

 

 

0 Kudos
0 Replies