Bug: Vitis-HLS 2020.2: RAM_1P-Interface not possible when disaggregating a input-struct
The goal is to read sequentially from a BRAM within two cycles (II=2) from a single port. If the config-struct is packed (by default with Vitis-HLS), this works fine. However, if you split the struct with Disaggregate-Pragma, a dual-port interface is generated. This means that the BRAM is now read in parallel in the same cycle instead of sequentially with one port as desired.
Remove #pragma HLS DISAGGREGATE to see the difference. In the attachment the source code with build script is linked. I am using Vitis 2020.2.