C/RTL CoSimulation is taking too much time.

[bkushal]

I have been trying to implement the example code in HLS given in UG 871: High-level synthesis tutorial –>tutorial 1, Lab1.

Project name- fir_prj.

System configuration

OS- windows 10

Vivado version- 2019.1

RAM- 16 GB

I was able to compile and synthesize (till step 3 as recommended in the UG871) the code successfully without any error or delay in Vivado HLS.

As for stage 4 is, that is C/RTL CoSimulation (RTL verification) it starts but it never ends until I terminate it. I tried with simple math code of addition and repeated the steps, still was not able to pass the test.

Once it reaches at this stage-

*************console window*************************************

source xsim.dir/fir/xsim_script.tcl

# xsim {fir} -autoloadwcfg -tclbatch {fir.tcl}

Vivado Simulator 2019.1

**************************************************

It is continuously running. What could be the issue?

Any help would be appreciated!

[shameera]

Hi @bkushal ,

Are you seeing the Infinite runtime for the RTL simulation only for this project, I mean only for fir_prj or with all the projects ?

Can you try running RTL simulation on any other example project and share the outcome ?

[bkushal]

Hi @shameera ..

Are you seeing the Infinite runtime for the RTL simulation only for this project, I mean only for fir_prj or with all the projects?--> Yes! I tried with 2 different projects- 

1. A simple 'and-gate' code in c. 

2. a simple arithmetic code in which a constant value is being added to an array/vector. 

for any project I run, It is taking infinite runtime for RTL simulation.

for and gate code- the the simulation process gets stuck at this step-

*******************console window**************************

source xsim.dir/and_gate/xsim_script.tcl
# xsim {and_gate} -autoloadwcfg -tclbatch {and_gate.tcl}
Vivado Simulator 2019.1

**************************************************************************

please find the attached screenshot.

[nithink]

Can you share your simple example?

Thanks,

Nithin

[shameera]

Hi @bkushal ,

Thanks for checking and confirming that any project is taking more time for RTL simulation.

Can you just invoke vivado and try running simulation for any RTL design there and let us know the outcome.

[bkushal]

@nithink 

Yes sure. I am sharing you the 'and_gate' code with its test bench. 

Kindly note I am a beginner in C.

attaching both the codes here-

***************************************Source code***********************************************************************************************************************

#include <stdio.h>
#include<hls_math.h>

//int and_gate(int a, int b, int c)

int a,b,c;

void and_gate(int a, int b, int c)
{


//#pragma HLS INTERFACE =res
//#pragma HLS INTERFACE bram port=a


//#pragma HLS RESOURCES variable= input core = AXIS metadata= "-bus bundle a"
//#pragma HLS RESOURCES variable= input core = AXIS metadata= "-bus bundle b"

//#pragma HLS RESOURCES variable= output core = AXIS metadata= "-bus bundle c"

#pragma HLS INTERFACE axis port=a
#pragma HLS INTERFACE axis port=b

#pragma HLS INTERFACE axis port=c

c = a & b; // bitwise-and operation
// return c;
}

**************************************************************************************************************************************************************

***********************************************test bench***************************************************************************************************************

//-------------------------------test bench-------------------------------------------------------

#include <stdio.h>
//#include <AND_gate_source_h.h>

//#include "and_gate_source.cpp"

//int and_gate (int a, int b, int c); // calling the and_gate function
void and_gate (int a, int b, int c);

int main()
{
int x,y;
int j,c=0b00;

printf("\n Test Initiated");

for (j=0; j<4;j++)
{
switch(j)
{
case 0:
x=0b00;
y=0b00;
break;
case 1:
x=0b00;
y=0b01;
break;
case 2:
x=0b01;
y=0b00;
break;
case 3:
x=0b01;
y=0b01;
break;
default:
printf("\nerror!");
}

and_gate(x ,y, c);

printf("\nresult:%d",c);
}
}

*****************************************************************************************************************************************************************

[bkushal]

Hi @shameera 

Can you just invoke vivado and try running simulation for any RTL design there and let us know the outcome.-> Yes, I did. I wrote a VHDL code for 'and_gate' and run the simulation in vivado. For this as well, I am seeing the infinite runtime for simulation. 

attaching the screenshot.

[bkushal]

Can you just invoke vivado and try running simulation for any RTL design there and let us know the outcome.-> Yes, I did. I wrote a VHDL code for 'and_gate' and run the simulation in vivado. For this as well, I am seeing the infinite runtime for simulation. 

attaching the screenshot.

[nithink · Accepted solution]

Hi,

  Your output is unconnected. The output should be either a pointer or a reference if it's a scalar for HLS to synthesize it as expected.

If you just make this change in your code, it will work

int& c

Thanks,

Nithin

[aoifem]

Hi @bkushal 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

[bkushal]

I tried doing that. Thank you for your suggestion. I skipped the RTL co-simulation and proceded, my and gate code worked on hardware.

But however the C/RTL Co-simulation is still taking infinite run time. 

[nithink]

Hi,

  Have attached the modified files and tcl file to run HLS. You can see that co-sim completed without any hang.

To rerun

% vivado_hls -f run_hls.tcl

Thanks,

Nithin

[aoifem]

Hi @bkushal 

Do you have any update on the status of this? 

Regards,