cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
9,663 Views
Registered: ‎08-06-2015

C/RTL Cosimulation hangs

Hello,

 

I am using Vivado HLS 2015.4 for my project. C simulation and synthesis are successful, but cosimulation hangs for hours. There are no any warning messages during hanging. In addition, I didn't use any stream in my code.

 

What should I do to start debugging ?

 

xsim.log

#-----------------------------------------------------------
# xsim v2015.4 (64-bit)
# SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
# IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
# Start of session at: Wed Mar 30 20:08:57 2016
# Process ID: 1080
# Current directory: C:/Users/Kit/Desktop/ba_hls/bundle_adjustment_hls/opt/sim/vhdl
# Command line: xsim.exe -mode tcl -source {xsim.dir/ba_top/xsim_script.tcl}
# Log file: C:/Users/Kit/Desktop/ba_hls/bundle_adjustment_hls/opt/sim/vhdl/xsim.log
# Journal file: C:/Users/Kit/Desktop/ba_hls/bundle_adjustment_hls/opt/sim/vhdl\xsim.jou
#-----------------------------------------------------------
source xsim.dir/ba_top/xsim_script.tcl
# xsim {ba_top} -maxdeltaid 10000 -autoloadwcfg -tclbatch {ba_top.tcl}
Vivado Simulator 2015.4
Time resolution is 1 ps
source ba_top.tcl
## run all
Note: 
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note: 
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note: 
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note: 
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note: 
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note: 
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note: 
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0

 

0 Kudos
4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
9,658 Views
Registered: ‎10-24-2013

Hi @kit947

 

We have seen similar issues before and adding the following line after solution is set may get the test passed.
config_dataflow -default_channel fifo -fifo_depth 200000

If you have ap_fifo without depth defined, please check the following AR.

http://www.xilinx.com/support/answers/60314.html

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Highlighted
Observer
Observer
9,643 Views
Registered: ‎08-06-2015

Thank you for your reply @vijayak

 

I tried your solution, but it doesn't work, and still stucks in the same place. After that, I have also removed all dataflow directives and ap_fifo port, but the same issue occurs.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
9,593 Views
Registered: ‎10-24-2013

Hi @kit947

 

Can you please attach the project arvhice here?

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Highlighted
Advisor
Advisor
9,577 Views
Registered: ‎04-26-2015

How complex is the module? I've had a few that take hours for cosim, simply because they're really complex and cosim is slow. This is obviously very annoying because you're never sure whether it's actually locked up completely, or whether it's just taking a while.

 

Sometimes it's worth just pushing the module into hardware for testing; if it takes more than a second on the FPGA then you can be pretty sure that it's never going to complete and go looking for bugs.

 

The one that I've encountered most frequently is allowing HLS to use internal streams - although that shouldn't happen without the dataflow directive.

0 Kudos