UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
284 Views
Registered: ‎10-02-2018

C Simulation and C/RTL Simulation produce different results

Greetings everyone,
I am trying to design a convolution layer in C++, using Vivado HLS 2017.4. During testing, both simulations produced different results and I cannot for the life of me figure out why.

Doing the maths by hand, the C Simulation presents the correct result, but there shouldn't have been a difference regardless.

//Convolution layer
#define IMAGE(C, I, J) (map[(I)*IMAGE_WIDTH+(J) + (IMAGE_WIDTH*IMAGE_HEIGHT*C)]) #define KERNEL(O,C,I,J) (kernel[(I)*KERNEL_WIDTH+(J) + (KERNEL_WIDTH*KERNEL_HEIGHT*((C)))]) //this had a [O][...] before. #define OUT(O, I) (output[(O*OUTPUT_HEIGHT*OUTPUT_WIDTH) + I]) //It should not be an int but a single bit, it occupies less space that way. For testing //purposes it will start off like so. template <int bit> int conv_element(float map[], float kernel[], float output[], int IMAGE_HEIGHT,\ int KERNEL_HEIGHT, int OUTPUT_HEIGHT, int IMAGE_WIDTH, int KERNEL_WIDTH,\ int OUTPUT_WIDTH, int INPUTS, int OUTPUT) { int i, j, chan, k, l; int s = 0; float image, kern, bias, accum = 0; for(int i = 0; i < (IMAGE_HEIGHT - KERNEL_HEIGHT + 1); i++) { for(int j = 0; j < (IMAGE_WIDTH - KERNEL_WIDTH + 1); j++) { accum = 0; for(int chan = 0; chan < INPUTS; chan++) { for(int k = 0; k < KERNEL_HEIGHT; k++) { for(int l = 0; l < KERNEL_WIDTH; l++) { image = IMAGE(chan, (i+k), (j+l)); kern = KERNEL(OUTPUT, chan, k, l); //and the bias macro, that also needs to be a thing I am not testing //at the moment. //printf("map: %f, kernel: %f\n", image, kern); accum += image*kern; } } } //printf("accum: %f\n", accum); //Need to define an output access macro, in order to write //the results to it. //For now, no macro. output[(OUTPUT*9)+s++] = accum; } } return 1; } template <int bit> void convolution(VSTREAM &input, float map[], float kernel[][18], \ float output[], int IMAGE_HEIGHT,\ int KERNEL_HEIGHT, int OUTPUT_HEIGHT, int IMAGE_WIDTH, int KERNEL_WIDTH,\ int OUTPUT_WIDTH, int INPUTS, int OUTPUTS, int KERNELS) { int o; //Need some checks for the initial reception. for(int o = 0; o < KERNELS; o++) { printf("%d\n", KERNEL_HEIGHT*KERNEL_WIDTH*INPUTS); rec(input, kernel[o], (KERNEL_HEIGHT*KERNEL_WIDTH*INPUTS)); } for(int o = 0; o < OUTPUTS; o+=KERNELS) { //Possibility of unrolling this loop rather than having this done by hand. //Check it out ASAP. if(o < OUTPUTS) { conv_element<1>(map, kernel[0], output, IMAGE_HEIGHT, KERNEL_HEIGHT, OUTPUT_HEIGHT, IMAGE_WIDTH, KERNEL_WIDTH,\ OUTPUT_WIDTH, INPUTS, o); if((o+KERNELS) < OUTPUTS) rec(input, kernel[0], (KERNEL_HEIGHT*KERNEL_WIDTH*INPUTS)); } if((o+1) < OUTPUTS) { conv_element<2>(map, kernel[1], output, IMAGE_HEIGHT, KERNEL_HEIGHT, OUTPUT_HEIGHT, IMAGE_WIDTH, KERNEL_WIDTH,\ OUTPUT_WIDTH, INPUTS, o+1); if((o+1+KERNELS) < OUTPUTS) rec(input, kernel[0], (KERNEL_HEIGHT*KERNEL_WIDTH*INPUTS)); } } return; }
//Testbench
#define IMAGE_HEIGHT 5 #define IMAGE_WIDTH 5 #define IMAGE_SIZE (IMAGE_HEIGHT*IMAGE_WIDTH) #define KERNEL_HEIGHT 3 #define KERNEL_WIDTH 3 #define KERNEL_SIZE (KERNEL_HEIGHT*KERNEL_WIDTH) #define OUTPUT_SIZE 3*3 int main() { VSTREAM input_stream, output_stream; struct ap_axis pixel; int i; printf("This is my image.\n"); for(i = 1; i <= IMAGE_SIZE; i++) { pixel.data = i/1.0; printf("%f; ", pixel.data); input_stream << pixel; } printf("\nThis is my kernel.\n"); for(i = 1; i <= KERNEL_SIZE; i++) { pixel.data = i/1.0; printf("%f; ", pixel.data); input_stream << pixel; } printf("\n"); network(input_stream, output_stream); printf("This is the output.\n"); for(i = 0; i < 9; i++) { output_stream >> pixel; printf("%f\n", pixel.data); } return 0; }
//End of the CSIM Log
INFO: [SIM 211-4] CSIM will launch GCC as the compiler. Compiling ../../../testbench.cpp in debug mode Compiling ../../../defs.cpp in debug mode Compiling ../../../network.cpp in debug mode Generating csim.exe This is my image. 1.000000; 2.000000; 3.000000; 4.000000; 5.000000; 6.000000; 7.000000; 8.000000; 9.000000; 10.000000; 11.000000; 12.000000; 13.000000; 14.000000; 15.000000; 16.000000; 17.000000; 18.000000; 19.000000; 20.000000; 21.000000; 22.000000; 23.000000; 24.000000; 25.000000; This is my kernel. 1.000000; 2.000000; 3.000000; 4.000000; 5.000000; 6.000000; 7.000000; 8.000000; 9.000000; 9 This is the output. 411.000000 456.000000 501.000000 636.000000 681.000000 726.000000 861.000000 906.000000 951.000000 INFO: [SIM 211-1] CSim done with 0 errors. INFO: [SIM 211-3] *************** CSIM finish *************** Finished C simulation.
//End of the Cosim Log
INFO: [Common 17-206] Exiting xsim at Thu Mar 14 18:54:13 2019... INFO: [COSIM 212-316] Starting C post checking ... This is my image. 1.000000; 2.000000; 3.000000; 4.000000; 5.000000; 6.000000; 7.000000; 8.000000; 9.000000; 10.000000; 11.000000; 12.000000; 13.000000; 14.000000; 15.000000; 16.000000; 17.000000; 18.000000; 19.000000; 20.000000; 21.000000; 22.000000; 23.000000; 24.000000; 25.000000; This is my kernel. 1.000000; 2.000000; 3.000000; 4.000000; 5.000000; 6.000000; 7.000000; 8.000000; 9.000000; This is the output. 324.000000 361.000000 408.000000 549.000000 596.000000 643.000000 784.000000 831.000000 878.000000 INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***

Apologies for the large chunks of code. The full project is in the attached zip, it should compile and run with no problems.

0 Kudos
2 Replies
Moderator
Moderator
239 Views
Registered: ‎05-31-2017

Re: C Simulation and C/RTL Simulation produce different results

Hi @miguel.cardoso ,

I tried to run the attached design in Vivado HLS 2018.3 and I don't see any issues at my end as CSIM and RTL SIM are exactly matching.

CSIM snippet:-

CSIM.JPG

RTL SIM Snippet:-

RTL_SIM.JPG

0 Kudos
227 Views
Registered: ‎10-02-2018

Re: C Simulation and C/RTL Simulation produce different results

That is very weird. I am reticent to update to 2018.3, but perhaps I should.

Thank you for the assist.
0 Kudos