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jhorswill
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Registered: ‎10-08-2020

C synthesis reports different initiation interval to C/RTL cosim

Hi there, thanks for taking the time to read my post.

I have an issue with the discrepancy between my design's performance in the synthesis report and the C/RTL co-simulation report.

Without interface directives, my block pipelines to a latency of 4 and II = 1 in both the synthesis and C/RTL reports.

When I apply axis directives to my design, the synthesis report the same performance as before, except the RTL cosimulation reports differently, as seen below:

Screenshot from 2021-04-21 23-13-48.pngScreenshot from 2021-04-21 23-13-59.png

The design consists of one input struct port and one output struct port defined as:

struct ap_axi4s{
	    ap_int<16>    data;
	    ap_uint<2>    keep;
	    bool    user;
	    bool    last;
};

// Declared as:
void fir_HLS_axi4s_simplified(ap_axi4s tdata_i, ap_axi4s* tdata_o);

 with directive.tcl:

set_directive_pipeline -II 1 "fir_HLS_axi4s_simplified"

set_directive_interface -mode axis -register -register_mode both -depth 1 -name s_axis_data "fir_HLS_axi4s_simplified" tdata_i
set_directive_interface -mode axis -register_mode off -depth 1 -name m_axis_data "fir_HLS_axi4s_simplified" tdata_o


set_directive_data_pack "fir_HLS_axi4s_simplified" tdata_i
set_directive_data_pack "fir_HLS_axi4s_simplified" tdata_o

This massive difference in performance is causing issues in my Questasim simulation. Does anyone know how this can happen, and how to fix it? I need a strict II = 1 (not a maximum of 2) for my design.

For reference, when I set register mode 'off' for both input and output axis ports, the cosim gives latency = 4 and II = 1, but this is not an operational design; at least one axis port needs registers assigned.

Screenshot from 2021-04-21 23-13-59.png
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