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ransaraw
Newbie
Newbie
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Registered: ‎06-26-2021

CNN using HLS; C simulation error

"I am totally new to FPGAs and High level synthesis, I have a very little amount of C programming experience and knowledge."

 

I am trying to implement a CNN on FPGA using the code supplied by the following blog.

https://www.amiq.com/consulting/2020/03/05/cnn-using-hls/

The code's git repository.

https://github.com/amiq-consulting/CNN-using-HLS

 

It is written for Vivado HLS 2018.3, however I am trying to implement it on Vitis HLS 2020.2.

I have done the changes in file includes to include the hls_stream.h and since the program uses LineBuffer, I have included "C:/Xilinx/Vitis/2020.2/include/multimediaIps/xf_video_mem.hpp" as well.

In the individual modules they have provided, doing the above changes lead to successful C simulation and synthesis in each one of them.

However in the nnet_stream where everything is put together, it produces the following error in C simulation.

Console output.

Starting C simulation ...
C:/Xilinx/Vitis_HLS/2020.2/bin/vitis_hls.bat C:/Users/menuw/Documents/research/BNN/trials/CNN-HLS/CNN-using-HLS-master/nnet_stream/neural_net/no_directives/csim.tcl
INFO: [HLS 200-10] Running 'C:/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/win64.o/vitis_hls.exe'
INFO: [HLS 200-10] For user 'menuw' on host 'ransara-laptop' (Windows NT_amd64 version 6.2) on Sat Jun 26 14:44:12 +0530 2021
INFO: [HLS 200-10] In directory 'C:/Users/menuw/Documents/research/BNN/trials/CNN-HLS/CNN-using-HLS-master/nnet_stream'
Sourcing Tcl script 'C:/Users/menuw/Documents/research/BNN/trials/CNN-HLS/CNN-using-HLS-master/nnet_stream/neural_net/no_directives/csim.tcl'
INFO: [HLS 200-1510] Running: open_project neural_net
INFO: [HLS 200-10] Opening project 'C:/Users/menuw/Documents/research/BNN/trials/CNN-HLS/CNN-using-HLS-master/nnet_stream/neural_net'.
INFO: [HLS 200-1510] Running: set_top nnet
INFO: [HLS 200-1510] Running: add_files nnet.cpp
INFO: [HLS 200-10] Adding design file 'nnet.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb nnet_test.cpp -cflags -I../../../../../../../../../Xilinx/Vitis/2020.2/include -DHW_COSIM -Wno-unknown-pragmas -csimflags -Wno-unknown-pragmas
INFO: [HLS 200-10] Adding test bench file 'nnet_test.cpp' to the project
INFO: [HLS 200-1510] Running: open_solution no_directives -flow_target vivado
INFO: [HLS 200-10] Opening solution 'C:/Users/menuw/Documents/research/BNN/trials/CNN-HLS/CNN-using-HLS-master/nnet_stream/neural_net/no_directives'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xc7z020-clg400-1
INFO: [HLS 200-1510] Running: create_clock -period 10 -name default
INFO: [HLS 200-1510] Running: csim_design -clean -quiet
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../nnet_test.cpp in debug mode
Compiling ../../../../nnet.cpp in debug mode
csim.mk:78: recipe for target 'obj/nnet.o' failed
In file included from C:/Xilinx/Vitis_HLS/2020.2/include/floating_point_v7_0_bitacc_cmodel.h:144:0,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_fpo.h:189,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half_fpo.h:64,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half.h:71,
from C:/Xilinx/Vitis_HLS/2020.2/include/etc/ap_private.h:91,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_common.h:646,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_fixed.h:55,
from ../../../../nnet_test.cpp:26:
C:/Xilinx/Vitis_HLS/2020.2/include/gmp.h:63:0: warning: "__GMP_LIBGMP_DLL" redefined
#define __GMP_LIBGMP_DLL 0

In file included from C:/Xilinx/Vitis_HLS/2020.2/include/hls_fpo.h:189:0,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half_fpo.h:64,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half.h:71,
from C:/Xilinx/Vitis_HLS/2020.2/include/etc/ap_private.h:91,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_common.h:646,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_fixed.h:55,
from ../../../../nnet_test.cpp:26:
C:/Xilinx/Vitis_HLS/2020.2/include/floating_point_v7_0_bitacc_cmodel.h:136:0: note: this is the location of the previous definition
#define __GMP_LIBGMP_DLL 1

In file included from C:/Xilinx/Vitis_HLS/2020.2/include/floating_point_v7_0_bitacc_cmodel.h:144:0,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_fpo.h:189,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half_fpo.h:64,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half.h:71,
from C:/Xilinx/Vitis_HLS/2020.2/include/etc/ap_private.h:91,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_common.h:646,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_fixed.h:55,
from ../../../../headers/weights.h:24,
from ../../../../nnet.cpp:22:
C:/Xilinx/Vitis_HLS/2020.2/include/gmp.h:63:0: warning: "__GMP_LIBGMP_DLL" redefined
#define __GMP_LIBGMP_DLL 0

In file included from C:/Xilinx/Vitis_HLS/2020.2/include/hls_fpo.h:189:0,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half_fpo.h:64,
from C:/Xilinx/Vitis_HLS/2020.2/include/hls_half.h:71,
from C:/Xilinx/Vitis_HLS/2020.2/include/etc/ap_private.h:91,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_common.h:646,
from C:/Xilinx/Vitis_HLS/2020.2/include/ap_fixed.h:55,
from ../../../../headers/weights.h:24,
from ../../../../nnet.cpp:22:
C:/Xilinx/Vitis_HLS/2020.2/include/floating_point_v7_0_bitacc_cmodel.h:136:0: note: this is the location of the previous definition
#define __GMP_LIBGMP_DLL 1

make: *** [obj/nnet.o] Error 1
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 9.503 seconds; current allocated memory: 191.568 MB.
4
while executing
"source C:/Users/menuw/Documents/research/BNN/trials/CNN-HLS/CNN-using-HLS-master/nnet_stream/neural_net/no_directives/csim.tcl"
invoked from within
"hls::main C:/Users/menuw/Documents/research/BNN/trials/CNN-HLS/CNN-using-HLS-master/nnet_stream/neural_net/no_directives/csim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$newargs"
(procedure "hls_proc" line 16)
invoked from within
"hls_proc [info nameofexecutable] $argv"
Finished C simulation.

 

I found that DLL redifine error can be ignored.

I've attached my version of the project(cloned from the above git repo,edited the includes) without the generated solution files.

I sense that this maybe a very simple error and I lack the knowledge in C programming. I have been searching for a solution for about 2 days now, I cannot find where the error exactly is. Can someone please help me out in this situation.

Thank you very much.

 

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