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Anonymous
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Can external ADC sampling be done using C/C++ or systemC in VivadoHLS or SDSoc

hi ,

 

I'm a software engineer, and has no experience with FPGA RTL design. I have a project that need to sampling data from an external ADC chip connected to zynq 7020 chip, the sampled data need to be read from zynq internal ARM processor to do simple process and show in Qt UI apps.

 

I found that xilinx says vivado HLS or the newer SDSoc can do fpga design in C/C++, but every example I found is that, such a design is just speeding up the original c/c++ software code, most of the design is just algorithm application.

 

So, my question is , can I do AD sampling (external ADI adc chip) with zynq using vivado HLS or SDSoc  with C/C++ languages, for the whole system design? 

 

if c or c++ can do such a thing without using verilog or VHDL, then the zynq and new xilinx soc can be called with software-defined, and can be called "All programable".

 

Did I made very basic mistakes? 

 

by the way, is there any example for my project requirement?  I need the fpga get adc sampling data from external AD chip for 1Mbit/s and pass to arm processor for simple computing and show in Qt app, the example I want is just about the fpga, 

which get data from AD chip and pass to the ARM address space, and I can read data simply by reading a specified address.

 

Thanks in advance!

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Advisor
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Registered: ‎04-26-2015

Re: Can external ADC sampling be done using C/C++ or systemC in VivadoHLS or SDSoc

That should be possible. HLS is not exactly ideal for low-level interfacing, but if the ADC is connected over SPI, I2C, or parallel then the AXI SPI, I2C, or GPIO blocks will handle that. Then a HLS AXI Master can read data from the ADC through those, and a separate AXI Master can write it to system RAM.

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Anonymous
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Re: Can external ADC sampling be done using C/C++ or systemC in VivadoHLS or SDSoc

Thanks for the reply!

Actually I real want the low-level interfacing. The ADC has a parallel interface and is not common.

SPI, IIC, GPIO is not suitable as the ADC sampling rate is high, 3M sps.

maybe current stage of HLS is just for high-level IP interfacing and integration, which is called system-level.

thanks very much, I think I still need to learn verilog or VHDL.
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