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Visitor
Visitor
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Registered: ‎10-30-2020

Can't import HLS packaged RTL module into block design

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Hi experts,

I'm trying to import a RTL module into block design, but Vivado says this module is incompatible.

This RTL module contains a packaged HLS ip. When I expand the ip hierarchy, I found that an instance called xil_defaultlib.floating_pointxxxx can't be resolved. I think this issue prevents the RTL module from being imported into bd.

What's even more strange, this top level RTL can be synthesised successfully.

Could anyone help me out here?

mod.PNGhier.PNG

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blank
Visitor
Visitor
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Registered: ‎10-30-2020

For those who also meet this problem:

I figured it out.

To instantiate HLS IP in RTL, I should not directly include the RTL from HLS IP pakage folder into the vivado project.

Instead, find the HLS IP in IP catalog, doulbe click it, customize it. Then <my_hls_ip>.xci will be added to the project. Generate outputs for this ip, then we can instantiate this IP in RTL now.

View solution in original post

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aoifem
Moderator
Moderator
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Registered: ‎11-21-2018

Hi @blank 

There's a couple of things that might be going wrong here. 

1. When you created your IP in HLS, make sure the board you selected in HLS is the same as the board you selected in Vivado. There's a run through of this in the following tutorial: 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-7-Connecting-to-the-PS-using-AXI4-Lite-and-Vitis-HLS/ba-p/1137753

2. Please try updating all the IP in your block design in Vivado. In Vivado GUI you can go to Tool-->Report-->Report IP status and update. There is more information about this in UG896. You could also try resetting the output products. More info here: https://www.xilinx.com/support/answers/57264.html#:~:text=Right%20click%20on%20the%20DB,and%20select%20Generate%20Output%20Products.

3. Xilinx only supports its IP library when matched with the correct version in Vivado. For example, 2019.2 HDMI core and 2019.2 Vivado. This is because all of the testing and qualification has been done this way. You may choose to use older IP in newer versions of the tool, but this flow is not supported. Please make sure your versions match. 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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blank
Visitor
Visitor
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Registered: ‎10-30-2020

Hi aoifem,

Thanks for your quick reply. But I'm afraid these are not the root cause.

1. I'm quite sure the device in Vivado matches that in HLS. I'm using Avelo U250. Besides, there won't be any problem if the HLS IP is added to the block design. Only if the HLS IP's RTL wrapper is added to block design as a RTL module, the issue showes.

2. I did so, but doesn't help. Acctually floating_point_v7_1_10 seems to be a blackbox instead of IP. 

3. Same as above. Since it's not an IP, I think this rule is not applicable.

Thanks

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blank
Visitor
Visitor
429 Views
Registered: ‎10-30-2020

For those who also meet this problem:

I figured it out.

To instantiate HLS IP in RTL, I should not directly include the RTL from HLS IP pakage folder into the vivado project.

Instead, find the HLS IP in IP catalog, doulbe click it, customize it. Then <my_hls_ip>.xci will be added to the project. Generate outputs for this ip, then we can instantiate this IP in RTL now.

View solution in original post

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