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Explorer
Explorer
773 Views
Registered: ‎02-08-2018

Cannot connect slave axilite of custom IP block in Vivado block design

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Hello,

  I have made a custom IP block in Vivado HLS where the top function inputs two AXI streams and two floating point numbers.  I have set the floating point numbers to s_axilite as below:

void GaussBlurAndDecim(AXI_STREAM &image_in, AXI_STREAM &image_out, float td_sigma, float td_decim)
{
//#pragma HLS inline off
#pragma HLS INTERFACE axis port=image_in
#pragma HLS INTERFACE axis port=image_out
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
#pragma HLS_INTERFACE s_axilite port=td_sigma bundle=CTRL_BUS
#pragma HLS_INTERFACE s_axilite port=td_decim bundle=CTRL_BUS

 

However, when I export the RTL design and open it in the Vivado block diagram, the two floating point arguments appear as simple 32-bit pins, and I have not been able to figure out how to connect these pins to the design without having some kind of routing errors or bitstream errors.  Attached is an image of how the custom IP block appears in the block diagram.

Any suggestions appreciated

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custom_IP.png
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1 Solution

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Adventurer
Adventurer
658 Views
Registered: ‎07-20-2017

Re: Cannot connect slave axilite of custom IP block in Vivado block design

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You can set the td_sigma and td_decim as axis ports. Then use Microblaze to write to DDR memory address and use a AXI DMA in you design to read from those memory addresses to you HLS IP.

Regards, abhidan@logictronix.com
Please mark the Answer as "Accept as solution" if information provided solves your query. Give Kudos if you think it was helpful and reply oriented.

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4 Replies
Moderator
Moderator
745 Views
Registered: ‎11-09-2015

Re: Cannot connect slave axilite of custom IP block in Vivado block design

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Hi @agailey,

As they are constant floating point numbers, you might want to use the constant IP to give them a value.

However you need to know the precision of the 32 bit number. This should be given in HLS.

Then you need to convert the number into a HEX number.

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
729 Views
Registered: ‎02-08-2018

Re: Cannot connect slave axilite of custom IP block in Vivado block design

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Thanks for the response.

I looked into the constant IP.  My concern is that the value of the port would not be modifiable from CPU.  The purpose of these ports was to allow the client CPU program to modify certain parameter values without the need to reprogram the FPGA.  In Vivado HLS, these two floating point values are input arguments in the top level function.

I did manage to map these two floating point values to memory by making a constraints file.  However, the question remains how the client CPU program on the Microblaze can modify these values.

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Moderator
Moderator
707 Views
Registered: ‎11-09-2015

Re: Cannot connect slave axilite of custom IP block in Vivado block design

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Hi @agailey,

If you need to modify these values from the CPU, you can use the AXI GPIO IP.

For a better solution, you might want to read deeply the HLS documentation and see how they can be implemented as registers (I do not know how to do that).


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
659 Views
Registered: ‎07-20-2017

Re: Cannot connect slave axilite of custom IP block in Vivado block design

Jump to solution

You can set the td_sigma and td_decim as axis ports. Then use Microblaze to write to DDR memory address and use a AXI DMA in you design to read from those memory addresses to you HLS IP.

Regards, abhidan@logictronix.com
Please mark the Answer as "Accept as solution" if information provided solves your query. Give Kudos if you think it was helpful and reply oriented.

View solution in original post

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