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Observer anujvaishnav
Observer
1,206 Views
Registered: ‎11-06-2017

Change data bus size for AXI interface when using OpenCL

Hi,

 

I am trying to get access to memory with more than 32 bits but it seems by default Vivado HLS tends to generate 32-bit bus for data access (and 32/64 bit bus for addresses). Is there any way to increase this to something like 128/256/512 wide data access?

 

I have attempted using custom data types from C lib of Vivado HLS but it seems that is incompatible with clc.h.

Also using datatypes like long2 does not change the interface width as per synthesis report. 

The HLS pragmas on the interface are also not allowed for OpenCL so we cannot go change the interface type either.

 

The board I am using is Zync Ultarscale+ (zcu102).

 

Any suggestions?

 

Many thanks,

Anuj

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3 Replies
Xilinx Employee
Xilinx Employee
1,202 Views
Registered: ‎07-18-2014

Re: Change data bus size for AXI interface when using OpenCL

Hi @anujvaishnav,

You can increase the data with using vectored datatype in openCL. Please refer below example for more details:

https://github.com/Xilinx/SDSoC_Examples/tree/master/ocl/getting_started/wide_mem_rw_ocl

 

-Heera

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Observer anujvaishnav
Observer
1,193 Views
Registered: ‎11-06-2017

Re: Change data bus size for AXI interface when using OpenCL

Hi @heeran,

 

Using the example from Repo, it still seems to be generating WDATA and RDATA of 32 bit rather than 128 bit (picture below).

I assume it reads the data in 32 bit chunk from memory and then starts processing it as whole 128 bit variable. 

 

Is there any way to change the 32 bit WDATA and RDATA in itself?

 

Regards,

Anuj

 

Screenshot from 2018-05-02 16-30-26.png

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Xilinx Employee
Xilinx Employee
1,002 Views
Registered: ‎06-20-2018

Re: Change data bus size for AXI interface when using OpenCL

Hi @anujvaishnav,

 

Using the same example in SDx 2018.2 release, it seems to be generating RDATA & WDATA OF 128 bits width (picture below). 

 

Regards,

Rajat

Capture.PNG
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