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witxilinx
Observer
Observer
637 Views
Registered: ‎12-26-2018

Compilation error for instantiating more than 4 modules accessing BRAM

Dear Developers,

I have `input`, `weight`, and `output` values, stored in arrays (with capacity 1024). These are going to be multiplied together: for every index `i`, output[i] = input[i]*weight[i]. Now I want to mytiply 8 pairs of (input,weight) at a time, so I am trying to instantiate 8 multiplier units as follow.

Question:

When running the C simulation, the compiler starts to give an error if I instantiate more than 4 multiplers. Why is it so? How can I solve this problem? Is it about having too many modules simultaneously accesing the BRAM?

void compute(
  ap_uint<8*16> input[1024][1],
  ap_uint<8*16> weight[1024][16],
  ap_uint<8*16> output[1024][1]
  ) {
// bram
#pragma HLS INTERFACE bram port = input
#pragma HLS INTERFACE bram port = weight
#pragma HLS INTERFACE bram port = output

#pragma HLS INTERFACE s_axilite port = return bundle = CONTROL_BUS
#pragma HLS RESOURCE variable = weight core = RAM_1P

#pragma HLS array_reshape variable = input complete dim = 2
#pragma HLS array_reshape variable = weight complete dim = 2
#pragma HLS array_reshape variable = output complete dim = 2

  static hls::stream<ap_uint<10> > dst_idx_queue[8];
  static hls::stream<ap_uint<10> > src_idx_queue[8];
  static hls::stream<ap_uint<10> > wgt_idx_queue[8];
  
  // Instantiate multiplier units
  multiplier(input, weight, output, dst_idx_queue[0], src_idx_queue[0], wgt_idx_queue[0]);
  multiplier(input, weight, output, dst_idx_queue[1], src_idx_queue[1], wgt_idx_queue[1]);
  multiplier(input, weight, output, dst_idx_queue[2], src_idx_queue[2], wgt_idx_queue[2]);
  multiplier(input, weight, output, dst_idx_queue[3], src_idx_queue[3], wgt_idx_queue[3]);

  // Problem starts here onward ...
  //    |
  //    v
  // multiplier(input, weight, output, dst_idx_queue[4], src_idx_queue[4], wgt_idx_queue[4]);
  // multiplier(input, weight, output, dst_idx_queue[5], src_idx_queue[5], wgt_idx_queue[5]);
  // ...

}

 

This is the output error:

...
WARNING: Hls::stream 'hls::stream<ap_uint<12> >.1' is read while empty, which may result in RTL simulation hanging. WARNING: Hls::stream 'hls::stream<ap_uint<12> >.9' is read while empty, which may result in RTL simulation hanging. WARNING: Hls::stream 'hls::stream<ap_uint<11> >.1' is read while empty, which may result in RTL simulation hanging. @E Simulation failed: SIGSEGV. ERROR: [SIM 211-100] CSim failed with errors. INFO: [SIM 211-3] *************** CSIM finish ***************
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1 Reply
scampbell
Moderator
Moderator
574 Views
Registered: ‎10-04-2011

Hello @witxilinx ,

For this type of segmentation fault problem, the location of the error typcially lies in the testbench. Can you provide an example design project containing testbench and all necessary files to show this error? 

Thank you,
Scott

 

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