cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
297 Views
Registered: ‎12-03-2019

Converting an hls::dds data output channel to an output stream (hls::stream)

Hello,

I am using the dds_mode_fixed example reference design (vivado hls 2019.2) and am trying to convert the module to output axi4-stream without any fifos. The DDS class (hls::DDS) run method outputs to an array structure and not to an hls::stream.

Originally I wanted to do something like in the hls::nco example, where there is a () operator defined, such that every call to the top function will write a new value to the stream (the testbench will read it from the stream):

 

void nco_top(hls::stream< ap_uint<ACCUM_WIDTH > > &pinc,
             hls::stream< ap_uint<ACCUM_WIDTH > > &poff,
             hls::stream< hls::t_nco_output_data<SUPER_SAMPLE_RATE, OUTPUT_WIDTH> > &outputVal) {

  static hls::nco<ACCUM_WIDTH,
    PHASE_ANGLE_WIDTH,
    SUPER_SAMPLE_RATE,
    OUTPUT_WIDTH,
    DUAL_OUTPUT_CMPY_IMPL,
    SINGLE_OUTPUT_CMPY_IMPL,
    SINGLE_OUTPUT_NEG_CMPY_IMPL
    > uut(INIT_PINC, INIT_POFF);

  uut(pinc, poff, outputVal);

} // end of function nco_top

but the hls::DDS class run method does not output to a stream. It outputs to an array. I tried to configure the hls::DDS ip to run for 128 samples (default) and then convert to a stream using a loop, which seems to work, but I also get write and read FIFOs (128 deep) inferred, which I don't want. The final objective is to do something with every sample (modulation), and my modulation waveform will be a quite a bit longer than 128 samples. I certainly don't want write\read fifos that are as deep as the modulation waveform inferred. Here's what I have right now (there is also an HLS DATAFLOW directive pragma for tx_top and HLS_PIPELINE directive pragma for the loop in the directives.tcl file):

 

 

//uint32_t reg_gain = 0x2;
//#define WAVEFORM_BUFFER_LENGTH 16384
//uint16_t waveform_buffer[WAVEFORM_BUFFER_LENGTH];

void tx_top(hls::stream< ap_fixed<26,26> >& strm_out) {
	#pragma HLS STREAM variable=strm_out
	#pragma HLS INTERFACE ap_ctrl_none port=return
	#pragma HLS INTERFACE axis port=strm_out

    // Create a DDS instance.
    static hls::DDS<config1> dds_tx;

    // Stream the cosine component.
	hls::ip_dds::out_data_sin_cos<config1> data_channel[config1::input_length];
	data_phase_t phase_channel[config1::input_length];
	dds_tx.run(data_channel, phase_channel);

	// Modulate and apply gain.
	//static ap_ufixed<16,16> waveform_buffer_index = 0;
	tx_top_label2:for (unsigned int i = 0; i < config1::input_length; i++) {
		//strm_out << data_channel[i].get_cos();// * waveform_buffer[waveform_buffer_index++] * reg_gain;
		strm_out << data_channel[i].get_cos();
		data_phase_t temp = phase_channel[i];
	}
}

What is the recommended way of outputing from hls::DDS IP, have access to every sample, and not get FIFOs inferred?

Thanks!

 

 

0 Kudos
0 Replies