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Observer dupont.louis
Observer
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Registered: ‎04-07-2013

CoreGenerator and HLS

Basically I'm wondering about the proper way to integrate a core generated by CoreGenerator into a HLS design. It seems to me that the only way to do that is to create an external interface for that core on the top module of the HLS design. I have 2 main issues with that approach:

  • I can't use a C/C++ Test Bench
  • HLS won't be able to perform any behavioural based optimizations (ex : if you use the DATAFLOW directive)

It seems to me like the proper way to merge these 2 tools would be to have CoreGenerator generating a C++ function along with the RTL description but as far as I can see there are no options to do that with the core I'm targeting  (fixed point FFT). Anybody knows if Xilinx has special recommendations to achieve this? Thanks.

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