03-19-2019 11:22 AM - edited 03-25-2019 07:50 AM
I'm working with a design consisting of a loop over data from several input memories. A few values are calculated from this input data, and the results are written to an output memory. This loop needs to be pipelined with II=1. Please find attached the relevant code. The project can be created and the C-simulation, C-synthesis, and C/RTL cosimulation run using project/script_TC.tcl. The main processing loop is labeled "stub_pairs" and is found in TrackletAlgorithm/TrackletCalculator.cpp. For reference, I'm working in Vivado HLS 2018.3.
Now, when the main loop is not pipelined, the design passes the C-simulation, the C-synthesis completes without error, and the resulting RTL passes the C/RTL cosimulation. When the main loop is pipelined with II=1, the design still passes the C-simulation, the C-synthesis still completes successfully, but the C/RTL cosimulation fails. And the failure is peculiar in that some of the data in the output memory matches the expected output, but for a later iteration (see example output at the bottom).
Is it expected that there can be designs that pass the cosimulation without pipelining, but then fail it when pipelining is enabled? And in any case, is there a way to avoid this failure while still enabling pipelining?
Example output from cosimulation:
Event: 0 TrackletParameter: reference computed 0x0813BBC6734D94019 0x0B52DE8645BDC400B matches second reference value 0x0B52DE8645BDC400B 0x01833AF06887E440BD matches fourth reference value 0x01822F54662EFC4047 0x0921FD105B5D0F8599 matches sixth reference value 0x01833AF06887E440BD 0x01BA30446BE7223FE5 matches eighth reference value 0x01B9158060F5ED8090 0x03C0CCC460A4004151 matches twelfth reference value 0x0921FD105B5D0F8599 missing 0x01B95544738A297FC2 missing 0x01BA30446BE7223FE5 missing 0x01BD429C6FAFCCC182 missing 0x040EC3D85353E2C269 missing 0x040FC4C85385D9C293 missing 0x03C0CCC460A4004151 missing Event: 1 TrackletParameter: reference computed 0x028829486093104147 0x028A27786033ECC1F4 matches second reference value 0x028A27786033ECC1F4 0x081E45D073B2F20690 matches third reference value 0x081E45D073B2F20690 0x0FB556307411C07F12 matches fourth reference value 0x0FB556307411C07F12 0x10B7035065773EBD5C matches sixth reference value 0x02C20EC86803F58083 0x01BCEF986365203E9B matches seventh reference value 0x10B7035065773EBD5C 0x0EAC582C8090037D9A matches eighth reference value 0x01BCEF986365203E9B missing 0x0EAC582C8090037D9A missing 0x0F3119887370D1FEAC missing 0x0F3221187516D1FEAC missing 0x1031F87468C5E23E7A missing 0x103200786A90E23E7A missing …
03-19-2019 11:36 AM
Check your logs/messages and see if it says II=1 is valid for your case... It may indicate II=2 (or seomthing) is required.
Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)
03-19-2019 11:43 AM
The logs indicate that II=1 is achieved, and I don't see anything about a higher initiation interval being required (see output snippet below).
INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'TrackletCalculator_L_1' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'stub_pairs'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 20. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 206.699 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation.
03-21-2019 07:43 AM
Any other ideas? I'm kind of at a loss as to what could be going wrong, or even how to debug this problem.