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soleil
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Registered: ‎01-06-2017

Creating an interrupt signal in HLS IP

Hi,

 

I am using HLS to build a custom IP (in the Zynq SoC). I want to add an interrupt to the IP so that when a stage of computations has been completed, the IP can signal the ARM core to send it the input for the next stage.

 

Right now the top-level function in my HLS code looks like:

 

void HLS_accel (AXI_VAL INPUT_STREAM[IN_SIZE], AXI_VAL OUTPUT_STREAM[OUT_SIZE])
{
#pragma HLS INTERFACE s_axilite port=return     bundle=CONTROL_BUS
#pragma HLS INTERFACE axis      port=OUTPUT_STREAM
#pragma HLS INTERFACE axis      port=INPUT_STREAM

Now to create an interrupt, can I add another argument (bool* interrupt) and include the directive (#pragma HLS INTERFACE ap_ctrl_none port=interrupt)to the top-level function as follows:

 

 

 

And then can I simply write to interrupt (interrupt = 1) whenever I want to set the interrupt?

 

 

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muzaffer
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Registered: ‎03-31-2012

@soleil currently HLS supports two kinds of interrupts already: ready & done. Ready interrupts seems to be what you want at least at an IP level. It indicates that the IP is ready for new input ie it could be signalled before done which means all operations are completed.

I haven't seen any way to add other interrupts to HLS IP which can be triggered for features outside of these two.

For this feature read page 114 of UG902 (v2016.4). 

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soleil
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Registered: ‎01-06-2017

@muzaffer Thank you for your response! It's very helpful. I went through the documentation on interfaces in UG902 On pg 112, it says: 

"After synthesis, Vivado HLS implements the ports in the AXI4-Lite port, as shown in the following figure. Vivado HLS creates the interrupt port by including the function return in the AXI4-Lite interface. You can program the interrupt through the AXI4-Lite interface."

My top-level function is:

void HLS_accel (AXI_VAL INPUT_STREAM[IN_SIZE], AXI_VAL OUTPUT_STREAM[OUT_SIZE])
{
#pragma HLS INTERFACE s_axilite port=return     bundle=CONTROL_BUS
#pragma HLS INTERFACE axis      port=OUTPUT_STREAM
#pragma HLS INTERFACE axis      port=INPUT_STREAM

So HLS generates a slave AXILite port with as shown in the diagram below:

s_axilite.png

 

Would you know how I can program in HLS to produce in interrupt using this AXILite port? If you could point me to a resource, that would be great!

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muzaffer
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Registered: ‎03-31-2012

@soleil >>  Would you know how I can program in HLS to produce in interrupt using this AXILite port? If you could point me to a resource, that would be great!

 

you already have it: ug902. Don't stop at page 112. Keep reading till 125 or so.

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soleil
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@muzaffer I went through the documentation and found info on using the generated drivers in the ARM code to program the interrupt. But I couldn't find anything on how to program the interrupt in HLS. I want to set the interrupt at various points in my HLS code. Do you know if and how this can be done?

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soleil
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Registered: ‎01-06-2017

Put simply, I want to set ap_ready in my C code in HLS. But ap_ready is only generated along with all of the other block level interface signals (ap_start, ap_done, etc.) after I synthesize the hardware from the code. Is there a way to manipulate ap_ready in the code?
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muzaffer
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Registered: ‎03-31-2012

@soleil As far as I know there is no way to add a new interrupt. HLS adds two standard interrupts (for ready & idle) and generates them on its own at the time it sees it. 

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muzaffer
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Registered: ‎03-31-2012

@soleil ap_ready is strictly for hls code generation and it wouldn't make sense for the IP to be able to control it. What we need is HLS to allow custom interrupts controlled by the generated code.

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soleil
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@muzaffer Sorry to bother you so much but I am a bit confused. Could you please clarify? I couldn't quite understand - "What we need is HLS to allow custom interrupts controlled by the generated code." How can this be done because you initially mentioned "As far as I know there is no way to add a new interrupt." Thanks again for your help.

 

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muzaffer
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@soleil what I meant is that we need a specific feature but it doesn't currently exist in HLS.
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simchask
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Registered: ‎11-23-2017

@soleil

You need your function to have a non-void return.

Then you will have the standard interrupts.

thomasdon
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Registered: ‎05-23-2011

Hi

 

I had nearly the same problem.

I wrote an IP core who needs 3 interrupt outputs.

This core isn´t triggert, it is running all the time (bit 7  - auto_restart ='1').

I solved it by generating several 1 Bit outputs and set them to '1' for one cycle, in all other cycles this signal is '0'.

One cycle of the IP core take 8 clock cycles.

 

If you would concat this signal to an interrupt input you sometimes need an IP core to mark this signal as an interrupt.

 

Kind regards

 

Thomas

 

 

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Registered: ‎04-14-2017

@thomasdon

Dou you have an example? it would be great!!

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thomasdon
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Registered: ‎05-23-2011

Hi

 

Because I used our compony name in the IP I couldn´t give you the IP directly.

But the source file is very short I made a screenshot of the file and the importent setting in the IP dialog.

 

The output has to made to an irq master interface.

 

Kind Regards

 

Thomas

 

 

IRQ_Mapper.png
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