07-28-2020 06:40 AM
I would like to build a custom ip in HLS and then use in ZCU102, Ultrascale+. Here are the steps that I take:
1- I have implemented the HLS ip (Matrix Multiplication) exactly similar to the description explained in XAPP1170 and exported the ip with no error in terms of timing or utilization.
2- I added the ip to the Vivado catalouge ip
3- My design in Vivado includes this HLS ip, AXI DMA, Ultrascale+, HPM port, HP port, smart connect.
4- I synthesize and implement the design and export the hardware, bitstream into the SDK.
5- In SDK, I used DMA to transfer data to the ip but it does not work. If I use polling DMA, it only waits to get response and it never succeeds. If I use interrupt, it also does not work. I used ILA to capture the input of the HLS ip and I see there is nothing arrives to the IP. It might be that I did not setup the ILA correctly by the way.
I attach my design, HLS ip, and also the SDK software to this post.Can anyone help me to find the issue? it seems rather straightforward but it is not working.
// THIS IS THE TOP LEVEL DESIGN THAT WILL BE SYNTHESIZED
#define MCR_SIZE 1024
void standalone_mmult (float A, float B, float C)
mmult_hw <float, 32>(A, B, C);
//void HLS_accel (AXI_VAL in_stream[2*MCR_SIZE], AXI_VAL out_stream[MCR_SIZE])
void HLS_accel (AXI_VAL INPUT_STREAM[2*MCR_SIZE], AXI_VAL OUTPUT_STREAM[MCR_SIZE])
#pragma HLS INTERFACE s_axilite port=return bundle=CONTROL_BUS
#pragma HLS INTERFACE axis port=OUTPUT_STREAM
#pragma HLS INTERFACE axis port=INPUT_STREAM
// HLS DEPRECATED MODE
// // Map ports to Vivado HLS interfaces
// #pragma HLS INTERFACE ap_fifo port=in_stream
// #pragma HLS INTERFACE ap_fifo port=out_stream
// // Map HLS ports to AXI interfaces
// #pragma HLS RESOURCE variable=in_stream core=AXIS metadata="-bus_bundle INPUT_STREAM"
// #pragma HLS RESOURCE variable=out_stream core=AXIS metadata="-bus_bundle OUTPUT_STREAM"
// #pragma HLS RESOURCE variable=return core=AXI4LiteS metadata="-bus_bundle CONTROL_BUS"
wrapped_mmult_hw <float, 32, 32*32, 4, 5, 5>(INPUT_STREAM, OUTPUT_STREAM);
08-04-2020 06:53 AM
I suspect that the AXI DMA is expecting an AXI-Stream bus with the extra "side-channel" signals (especially tlast and tkeep).
Go to UG902 and search for "side-channel".
When using an AXI-Stream with side-channels signals, you are responsible for properly handling the side-channel signals. Tvalid and Tready are handled automatically by the logic generated for the AXI-Stream Interface.
08-11-2020 05:34 AM
Thanks for the response.
Currently, I am generating the ip using HLS using the following pragma: pragma HLS INTERFACE axis port. Also I am triggering tlast through the push/pop stream functions that I attached. When the ip generate the last piece of data, it will let the push stream knows about it by assigning the tlast to '1'. Isn't this the right way of handling the handshakes?
The code that I am using is the same that is provided by the Xilinx. So I assume it should work out of the box with no hassle... but it seems it is not true..