UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant valato
Participant
1,868 Views
Registered: ‎09-29-2017

Custom reset AXI register

Jump to solution

I want to have possibility to reset some values via one register over AXI-Lite interface. I have following idea:

static int counter = 0;
void top(bool * reset /* ... other parameters */) {
#pragma HLS INTERFACE s_axilite port=reset bundle=CONTROL
if (*reset) {
*reset = false;
counter = 0;
}
/* some other processing */
}

Problem is that in this case HLS creates two AXI registers - reset_i and reset_o and when I set reset_i to true from Xilinx SDK, it remains true for all iterations of top.

How to signal to a filter that it should perform the reset of variables only once via AXI-Lite?

----- Please mark the post as an answer "Accept as solution" in case it helped to solve your problem. Give kudos in case the post guided you to the solution.
0 Kudos
1 Solution

Accepted Solutions
Voyager
Voyager
2,553 Views
Registered: ‎06-24-2013

Re: Custom reset AXI register

Jump to solution

Hey @valato,

 

but in this case you would need to alternate between true and false ...

you can ignore one state transition which also eliminates the need to know the current state.

 

... and remember the last state ...

you can get the current state from the register and just invert/negate it.

 

Can I do it in HLS the way most IPs (in VHDL) are done?

Unfortunately a lot of the nice tricks possible with AXI memory mappings are not available via HLS (yet).

 

As far as I know, the closest you can get is by using the ap_ack/ap_vld/ap_hs on a data input/output.

 

Best,

Herbert

-------------- Yes, I do this for fun!
0 Kudos
5 Replies
Voyager
Voyager
1,852 Views
Registered: ‎06-24-2013

Re: Custom reset AXI register

Jump to solution

Hey @valato,

 

The easiest way is to check for a change of a given register by keeping the previous value in a static variable.

 

Best,

Herbert

-------------- Yes, I do this for fun!
0 Kudos
Participant valato
Participant
1,849 Views
Registered: ‎09-29-2017

Re: Custom reset AXI register

Jump to solution

Yes, I though about this workaround but in this case you would need to alternate between true and false also in Xilinx SDK code and remember the last state. And XFilter_Set_reset_i(pfilter, 0) seems to me a bit confusing.

Can I do it in HLS the way most IPs (in VHDL) are done? XFilter_Set_reset(pfilter, 1) and when the IP acknowledges the register it owerwrites it with 0.

----- Please mark the post as an answer "Accept as solution" in case it helped to solve your problem. Give kudos in case the post guided you to the solution.
0 Kudos
Voyager
Voyager
2,554 Views
Registered: ‎06-24-2013

Re: Custom reset AXI register

Jump to solution

Hey @valato,

 

but in this case you would need to alternate between true and false ...

you can ignore one state transition which also eliminates the need to know the current state.

 

... and remember the last state ...

you can get the current state from the register and just invert/negate it.

 

Can I do it in HLS the way most IPs (in VHDL) are done?

Unfortunately a lot of the nice tricks possible with AXI memory mappings are not available via HLS (yet).

 

As far as I know, the closest you can get is by using the ap_ack/ap_vld/ap_hs on a data input/output.

 

Best,

Herbert

-------------- Yes, I do this for fun!
0 Kudos
Participant valato
Participant
1,813 Views
Registered: ‎09-29-2017

Re: Custom reset AXI register

Jump to solution

Thanks for your point of view. I agree with you. The more complicated IPs I try to develop in HLS the more I hit the limits of this language.

Here is the code snippet for others that will encounter this limitation:

 

static int counter = 0;
static bool lastReset = false;
void top(bool reset /* ... other parameters */) {
#pragma HLS INTERFACE s_axilite port=reset bundle=CONTROL
if (reset && !lastReset) {
counter = 0;
}
lastReset = reset;
/* some other processing */
}

But still there is a problem with PS and PL synchronization. In case this IP runs for many cycles (e.g. image processing) you have to be sure that last false value from PS was read by IP (wait for frame completion) before you can change it to true.

 

----- Please mark the post as an answer "Accept as solution" in case it helped to solve your problem. Give kudos in case the post guided you to the solution.
0 Kudos
Voyager
Voyager
1,727 Views
Registered: ‎06-24-2013

Re: Custom reset AXI register

Jump to solution

Yeah, I totally agree that there are some really unfortunate limitations to HLS, especially to the AXI-lite interface portions. A lot of nice tricks you can do like atomic actions, write triggers, status flags, etc won't work in HLS.

 

All the best,

Herbert

-------------- Yes, I do this for fun!
0 Kudos