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kmchiti
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Registered: ‎03-27-2019

DRAM access by HLS

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Hi,

how could i access to different part of external memory like DRAM by hls? i found out that we can access DRAM with memcpy() function and AXI interface. but i'll want to access to any addresses of DRAM.

thank you

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u4223374
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Registered: ‎04-26-2015

If you have an array or pointer on the top-level interface, and you assign that to use an AXI Master interface, then writing to that array will write into whatever address space is mapped to the block in Vivado. For a Zynq you can just give it the full 4GB address space, plug the AXI Master into a Zynq HP AXI Slave port, and freely write to anywhere you want in DRAM. Obviously if the Zynq is actually using the DRAM at the time then this is likely to cause some confusion - so be careful.

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u4223374
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Registered: ‎04-26-2015

If you have an array or pointer on the top-level interface, and you assign that to use an AXI Master interface, then writing to that array will write into whatever address space is mapped to the block in Vivado. For a Zynq you can just give it the full 4GB address space, plug the AXI Master into a Zynq HP AXI Slave port, and freely write to anywhere you want in DRAM. Obviously if the Zynq is actually using the DRAM at the time then this is likely to cause some confusion - so be careful.

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kmchiti
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Registered: ‎03-27-2019

thanks for your response 

how could i determine depth of AXI Master interface for 4GB address space in zynq?

for example i have an array and assign that AXI Master interface like this:

#pragma HLS INTERFACE m_axi port=input_array depth=50

 

 

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