[DRC INBB-3] Black Box Instances - OpenCL kernel from HLS
I'm trying to implement a design (in Vivado 2017.3) with some kernels written in OpenCL and synthesized in Vivado HLS 2017.3. When I launch the implementation, I come up with this error message related to my IP:
[DRC INBB-3] Black Box Instances: Cell 'base_zynq_i/kernel_gpu_opencl_0/inst/kernel_gpu_openclpcA_U8/kernel_gpu_opencl_ap_faddfsub_3_full_dsp_32_u/U0' of type 'base_zynq_kernel_gpu_opencl_0_0_base_zynq_kernel_gpu_opencl_0_0_base_zynq_kernel_gpu_opencl_0_0_base_zynq_kernel_gpu_opencl_0_0_base_zynq_kernel_gpu_opencl_0_0_floating_point_v7_1_4' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
A very similar error shows up with a different OpenCL kernel (i.e., different application), so I'm start thinking that it might be something related to the tools I'm using (Vivado 2017.3 + Vivado HLS 2017.3), after being updated to the new version.
Here is a picture of my block design:
Any advice on how to fix this issue would be highly appreciated.