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Observer
Observer
6,890 Views
Registered: ‎11-26-2014

Design empty after HLS synthesis

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I am a new user of Vivado HLS, I'm interested in generating RTL code from compute intensive sections of a c code, so I have taken  the code below, and synthetized with Vivado_HLS,  I  got no errors/warnings, but the report shows 0.0 timing estimation and no resource utilization. Am I missing something here, does it have to do with the coding style? I have done the same for another section of the code and it reports timing and utilization. 

 

EXAMPLE 1:

 

int main ( )
{
    int i, index, rev;
    int NumBits;
    for ( i=rev=0; i < NumBits; i++ )
    {
        rev = (rev << 1) | (index & 1);
        index >>= 1;
    }

    return rev;
}

 

Raul

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Xilinx Employee
Xilinx Employee
13,143 Views
Registered: ‎08-17-2011

Hi @joseraul

 

"int main()" is the C TB and you need another top level function. in your example there is none.

 

Also if you rename main to something else, as there are no input to your function and i'm guessing the output return value rev is constant and equal 0.

 

check UG902 and the many examples in the tool.

- Hervé

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Xilinx Employee
Xilinx Employee
13,144 Views
Registered: ‎08-17-2011

Hi @joseraul

 

"int main()" is the C TB and you need another top level function. in your example there is none.

 

Also if you rename main to something else, as there are no input to your function and i'm guessing the output return value rev is constant and equal 0.

 

check UG902 and the many examples in the tool.

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.

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Observer
Observer
6,888 Views
Registered: ‎11-26-2014

For reference I have taken the function below and after synthesis in Vivado_HLS it reports a latency of 194 clock cycles and an utilization of 320 luts.

 

EXAMPLE 2:

 

#define ROT32(x,n)    ((x << n) | (x >> (32 - n)))

int main( )
{
    long W[80];
    int i;
    //long temp, A, B, C, D, E, W[80];

    for (i = 16; i < 80; ++i) {
    W[i] = W[i-3] ^ W[i-8] ^ W[i-14] ^ W[i-16];

#ifdef USE_MODIFIED_SHA
    W[i] = ROT32(W[i], 1);
#endif
        //printf( "W[%i] = %li \n", i, W[i]);
    }
  return 0;
}

 

I have also tried to synthesize the function below, but as with EXAMPLE 1, the report shows 0 delay and 0 utilization. For both cases EXAMPLE 1 and 2 the verilog code generated doesn't  have always blocks.

 

int main()
{
       long x;
       int n = 0;
/*
** The loop will execute once for each bit of x set, this is in average
** twice as fast as the shift/test method.
*/
        if (x) do
              n++;
        while (0 != (x = x&(x-1))) ;
        return(n);
}

 

Any clue why this functions are not synthesizing usable verilog code?

 

Raul.

 

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Xilinx Employee
Xilinx Employee
6,882 Views
Registered: ‎08-17-2011

It looks like my previous answer wasn't clear.

1- int main() is the C TB function so you need to have another top level function otherwise you can't have a C TB to test your design; usually main() will call top() and top is the C function converted to HDL RTL.

2- your design returns 0 so you managed to create an IP that does spend some clock cycles doing something; it looks like a delay function.

 

Again please check UG902 or the tools tutorial and examples; here is a link for your convenience : http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug902-vivado-high-level-synthesis.pdf#nameddest=xDesignExamplesAndReferences

 

- Hervé

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Observer
Observer
6,870 Views
Registered: ‎11-26-2014

Yes, It was very clear :) , It looks like I posted the second part while you kindly answered my first post. I am looking at the documentation now. Thank you for pointing me in the right direction.

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Xilinx Employee
Xilinx Employee
6,858 Views
Registered: ‎08-17-2011

Awesome ;-)

Sorry I thought that message 3 (yours) was direct answer to message 2 (mine) so I wrote that message 4 :-D

- Hervé

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