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mdomingu
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Registered: ‎07-10-2018

Desing debugging tools

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Hello,

I would like to know how you debug designs in your professional life, I mean, I am supposed to debug a design which is not working right now, how a person which uses HLS and is agnostic of the hardware running behind is supposed to debug with tools like ModelSim and so on? Are there more tools than the ones showing the signals and all the hardware stuff?

I searched in the Xilinx manuals and I did not find anything...

Thank you,
Marc

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u4223374
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Registered: ‎04-26-2015

@mdomingu Not with putc, but it's very similar. Basically you have an AXI Master port on the block which acts exactly like a large array in C, and you write debugging information to that array (one character at a time, just like putc would). With the port on the block connected to either a MIG or the Zynq HP AXI Slave ports, this data will end up in system RAM at whatever address you specify in the block.

 

From a Zynq running bare-metal you can access that RAM directly. Running Petalinux, you'll need to use mmap to map a real memory space into the program's virtual memory space. Once that's done it again acts as a large array that you can read from.

 

I made a post here about debugging, although that used an AXI Stream. That requires something to collect the data from the stream and store it somewhere - either in RAM or process it directly.

 

For what it's worth, the first method (ILA) appears to be almost identical to SignalTap. You can certainly use that to poke around inside HLS blocks, but HLS blocks tend to be incredibly convoluted and hard-to-understand at the HDL level. This makes debugging them very difficult.

 

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u4223374
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Registered: ‎04-26-2015

I wouldn't try debugging any non-trivial HLS design with a normal HDL debugger. The two techniques I normally use are:

 

(1) Put an ILA core on there to verify that the data going into the block makes sense - no point spending weeks trying to fix your block when actually the problems is that you've configured a VDMA incorrectly.

 

(2) Add debugging outputs to the code, in the form of an AXI Master that writes debug data to RAM as the block runs, and then a bit of code (on the Zynq PS or a MicroBlaze) to retrieve that data in a more meaningful format. It's much like C printf-debugging, except that you've only got putc instead of printf...

mdomingu
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Registered: ‎07-10-2018

First of all thank you,

I think I am not capable to go fast with the first choice, but is the most interesting.
The second one seems pretty fast, can I write to the PL memory just with "putc"? Then how can I read this memory from the processor? I've been the whole course with an Altera FPGA and the debugging was pretty clear with SignalTap so I am a little bit lost right now...

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u4223374
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Registered: ‎04-26-2015

@mdomingu Not with putc, but it's very similar. Basically you have an AXI Master port on the block which acts exactly like a large array in C, and you write debugging information to that array (one character at a time, just like putc would). With the port on the block connected to either a MIG or the Zynq HP AXI Slave ports, this data will end up in system RAM at whatever address you specify in the block.

 

From a Zynq running bare-metal you can access that RAM directly. Running Petalinux, you'll need to use mmap to map a real memory space into the program's virtual memory space. Once that's done it again acts as a large array that you can read from.

 

I made a post here about debugging, although that used an AXI Stream. That requires something to collect the data from the stream and store it somewhere - either in RAM or process it directly.

 

For what it's worth, the first method (ILA) appears to be almost identical to SignalTap. You can certainly use that to poke around inside HLS blocks, but HLS blocks tend to be incredibly convoluted and hard-to-understand at the HDL level. This makes debugging them very difficult.

 

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