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1,204 Views
Registered: ‎10-06-2017

Difficulty accessing array over axilite

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Hi ,

We want to access(both read and write) an array (which is a parameter to a top level function) over AXILite bus. The function will read the array values and use
them in the code. We have coded a function with an array as a parameter.The array is mapped to AXILite. We then have generated a verilog IP from the HLS code.

The simulation/cosimulation of the DUT works fine. When we perform the Verilog simulation of the IP that is generated from HLS, we are not able to access the
array. If instead of passing array to the function, if we pass individuals variables as parameters and then assign them to an array which is internally declared inside
the function, then the verilog simulation of the generated IP works fine.(simulation and Co simulation anyways works).


As an example, consider the code as below:
A. The function axi_array_top_orig works in simulation and cosimulation, but when we use the IP generated from it for doing RTL level simulation, it does not work.
void axi_array_top_orig(stream < ap_uint<8> > &outstream , ap_uint<8> in_array[8])
{
#pragma HLS data_pack variable=outstream
#pragma HLS INTERFACE s_axilite port=return
#pragma HLS INTERFACE s_axilite port=in_array

static ap_uint<8> temp;

for(int i = 0 ; i < 8 ; i++)
{
temp = in_array[i] + 5;
outstream.write(temp);
}
}


B. The function axi_array_top_new2 works in simulation and simulation, and also the IP level RTL simulation works.

void axi_array_top_new2(stream < ap_uint<8> > &outstream ,
ap_uint<8> val0 , ap_uint<8> val1,
ap_uint<8> val2 , ap_uint<8> val3,
ap_uint<8> val4 , ap_uint<8> val5,
ap_uint<8> val6 , ap_uint<8> val7)
{
#pragma HLS data_pack variable=outstream
#pragma HLS INTERFACE s_axilite port=return

#pragma HLS INTERFACE s_axilite port=val0
#pragma HLS INTERFACE s_axilite port=val1
#pragma HLS INTERFACE s_axilite port=val2
#pragma HLS INTERFACE s_axilite port=val3
#pragma HLS INTERFACE s_axilite port=val4
#pragma HLS INTERFACE s_axilite port=val5
#pragma HLS INTERFACE s_axilite port=val6
#pragma HLS INTERFACE s_axilite port=val7

static ap_uint<8> temp;
static ap_uint<8> in_array[8];
in_array[0] = val0;
in_array[1] = val1;
in_array[2] = val2;
in_array[3] = val3;
in_array[4] = val4;
in_array[5] = val5;
in_array[6] = val6;
in_array[7] = val7;

 


for(int i = 0 ; i < 8 ; i++)
{
temp = in_array[i] + 5;
outstream.write(temp);
}

 

}


we are not able to understand this behavior. Instead of passing an array, we have to now pass individual elements of the array and later assign them to locally
declared array. For arrays with large sizes, this is very cumbersome.


Please let me know how to get over this problem.


I am attaching the hls code as well as the testbench code for this.

best regards,

-Mahesh



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Xilinx Employee
Xilinx Employee
630 Views
Registered: ‎09-04-2017

Re: Difficulty accessing array over axilite

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Hi Mahesh,

  The issue is with the ARVALID signal in the axi_wr_sm.v  file. This output is undriven. when you are using array, HLS is creating memory for this and the control signals are dependent on an internal signal generated on ARVALID. Since this is X, it gets propagated.

In axi_wr_sm.v you can initialize this output to zero

output reg arvalid=0,

Once this change is made, i can see the outputs as expected. 

 

Thanks,

Nithin

 

View solution in original post

12 Replies
Scholar u4223374
Scholar
1,177 Views
Registered: ‎04-26-2015

Re: Difficulty accessing array over axilite

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mahesh.barve@tcs.com wrote:


The simulation/cosimulation of the DUT works fine. When we perform the Verilog simulation of the IP that is generated from HLS, we are not able to access the array.


Can you elaborate on this? What happens when you try to access the array?

 

 

 

Voyager
Voyager
1,164 Views
Registered: ‎03-28-2016

Re: Difficulty accessing array over axilite

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mahesh.barve@tcs.com,

How are you accessing the AXI-Lite interface during the RTL simulation?  Are you using the Zynq-VIP core?  Are you using your own AXI-Lite driver module?

In my experience, I haven't seen any issues with using arrays in the AXI-Lite interface.  I have run several successful RTL simulations using the Zynq-VIP core to drive the HLS IP's AXI-Lite interface.

As a side note, I don't think you need the DATA_PACK directive for the "outstream" port as it is a stream of 8-bit integers.  The DATA_PACK is used when the port is defined to use a structure.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Moderator
Moderator
1,120 Views
Registered: ‎11-21-2018

Re: Difficulty accessing array over axilite

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Hi mahesh.barve@tcs.com , 

 

Do you have any updates on this? 

Were you able to make any progress? 

 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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1,013 Views
Registered: ‎10-06-2017

Re: Difficulty accessing array over axilite

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We are not using  Zynq-VIP core. We have written our own state machine for generating AXI Lite cycles.

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966 Views
Registered: ‎10-06-2017

Re: Difficulty accessing array over axilite

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Hi All,

Sorry for the delay in response. We are giving more details here.

We basically have 2 DUTs. These have been written in HLS. The HLS code is already shared in earlier post.


The names of the DUTs are
(1)axi_array_top_orig
(2)axi_array_top_new2

(1)In axi_array_top_orig DUT takes an array (in_array) as input on the AXILite interface. The DUT then computes
temp = in_array[i] + 5 ;
outstream.write(temp) ;
thus, the outstream will have values of in_array[i] + 5.
We performed the functional simulation, synthesis and cosimulation of the code, which all work correctly.
The verilog for this is generated when we use export IP option in Vivado HLS. We then perform the RTL simulation using generated verilog IP. When we read the
outstream values and observe them in the waveform, however, outstream values are not correct (they all are X). This seems to be a bug/issue in the HLS synthesis tool.


(2) In the axi_array_top_new2, instead of in_array, we send 8 variables to the DUT over axi Lite. These values are assigned to the in_array array inside the function.
Each of the element of the array is then read and number 5 is addded to each array element and output is written to output stream as in the following code
temp = in_array[i] + 5;
outstream.write(temp);
In this case, when we perform the RTL simulation of generated IP, the outstream values are observed to be correct ( i.e. in_array[i] + 5).

For RTL simulation, in both cases 1 & 2, we have used an axi_wr_sm.v (an axilite write state machine which acts as axilite master for generating axi write cycles for
programming values for in_array in case I and variables in case II.

We have attached the test bench and other files with this post.

We have created a test bench. The test bench is in the file axi_xilinx_top_TB.v. The test bench in turn calls the module axi_xilinx_top from the file
axi_xilinx_top.v . Axi_xilinx_top will instantiate the DUT and the AXI write state machine. The AXI write state machine is in the file axi_wr_sm.v.
We have set addresses in axi_wr_sm.v file in the array addr_array. These addresses are obtained from the hardware address file generated in Vivado HLS. The hardware
address file is generated in driver folder after exporting the IP(xaxi_array_top_orig_hw.h and xaxi_array_top_new2_hw.h). The data array (data_array) has the
corresponding data that is to be sent to the DUT. Note: The IP has to be enabled by setting the bit pattern as 81 at the address 00.

We then created a project in Vivado and imported the IP directory (generated after exporting IP in Vivado HLS) in Vivado. We also added the 3 files
axi_xilinx_top_TB.v, axi_xilinx_top.v and axi_wr_sm.v . we then set axi_xilinx_top_TB as the top by right clicking on it and clicking the option "set as top" in
vivado).

We then ran the simulation in vivado using the Run simulation option.

 

We have attached the waveform images that we observed for case I and Case II. we observe that in the case where the DUT is axi_array_top_orig, there is no output seen
for outstream(not_working.jpg).
While when the DUT is axi_array_top_new2 correct data is output on the outstream(working.jpg).
1. case where output is seen : working.jpg
2. case where no output is seen : not_working.jpg

we are using the following tool Versions:
Vivado: v2018.2.2(64bit)
Vivado HLS: v2017.3


We are stuck with this problem since for an application that we are developing, we need to send a large array over AXILIte to the DUT. Since we are not able to do it,
we are currently creating a large number of variables and sending the variables to the DUT over axilite.

Can someone please help us in this,
Awaiting reply,
-Mahesh

 

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Moderator
Moderator
870 Views
Registered: ‎05-31-2017

Re: Difficulty accessing array over axilite

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Hi mahesh.barve@tcs.com ,

I was trying to look at this issue. I have created a new HLS project with the axi_array.cpp and axi_array_tb.cpp files in vivado HLS and did set the axi_array_top_orig as top function.

I have synthesized it in HLS and tried to see the verilog files that are generated by HLS.

I see that the verilog files present under not_working directory in the shared zip file (axi_array_forum_query.zip) and the verilog files that has been generated at my end seems to be different.

So, have you modified the RTL files that are generated by Vivado HLS ?

In vivado HLS after running RTL simulation, I have opened the waveform viewer, from that I observe that the output signal is showing the values as shown in the below snippet

hls_del.PNG

If you have modified the RTL files generated by vivado HLS can you once try by creating a test bench for the Verilog files generated by vivado HLS without any modifications and let us know if you see the same issue.

853 Views
Registered: ‎10-06-2017

Re: Difficulty accessing array over axilite

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Hi @shameera ,

  I have not attached the verilog generated from the HLS code. I have given details about the verilog files inside the attached zip file in my earlier post. I request you to please go through my earlier post. Please revert back with any questions that you may have on them. I have not modified any of the verilog generated from HLS by Vivado HLS.

best regards,

-Mahesh

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Moderator
Moderator
764 Views
Registered: ‎05-31-2017

Re: Difficulty accessing array over axilite

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Hi mahesh.barve@tcs.com ,

A quick check, I see that you have clk and reset values being forced in your test bench. As you are seeing the issues only when using the input as an array and also I don't see issues while seeing the waveforms directly from Vivado HLS.

I assume the issue is with the testbench, I mean you have left the control signals of the interface without forcing any values i.e., I think we need to provide the signal for making the interface aware of the valid address/data information. 

Moderator
Moderator
706 Views
Registered: ‎11-21-2018

Re: Difficulty accessing array over axilite

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Hi mahesh.barve@tcs.com 

 

If your question is answered or your issue is solved, please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
658 Views
Registered: ‎10-06-2017

Re: Difficulty accessing array over axilite

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Hi,

We have still not been able to get over the problem.

It would be great if someone guides us in this.

regards,

-Mahesh

 

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Xilinx Employee
Xilinx Employee
631 Views
Registered: ‎09-04-2017

Re: Difficulty accessing array over axilite

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Hi Mahesh,

  The issue is with the ARVALID signal in the axi_wr_sm.v  file. This output is undriven. when you are using array, HLS is creating memory for this and the control signals are dependent on an internal signal generated on ARVALID. Since this is X, it gets propagated.

In axi_wr_sm.v you can initialize this output to zero

output reg arvalid=0,

Once this change is made, i can see the outputs as expected. 

 

Thanks,

Nithin

 

View solution in original post

573 Views
Registered: ‎10-06-2017

Re: Difficulty accessing array over axilite

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Thanks @nithink .

  The change that you suggested solved my problem.

thanks and best regards,

-Mahesh

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