12-02-2013 06:00 AM
i have a design which consists of a toplevel function and this one has many functions in it.
Each of this functions has static arrays where data is read at the beginn, and data is written to the same adress at the end of the function.
The toplevel funtion runs with an II of 1.
The same adress of an array is accessed only every 4. cycle.
How do i tell vivado, that i access on the same adress every 4. cycle?
I tried various combinations with the set directive dependence directive, but it didn't work.
I always get the message, that i read and write at the same time, when i run the c/rtl cosimulation..
12-02-2013 11:25 PM
12-03-2013 03:52 AM
Thanks for your reply!
Yes, i tried this already. But the design wasn't able to met the time requirements. I think they are simply to strict.
Another question: Can i tell VHLS, that in every clock cycle, writes are allowed only direct afters reads?
I want to improve the logic structure through the ressource directive. Is thery any document, which tells me how long certain operations take, with specific ressources?
I use distributed Ram as memory. Is it possible to read a value from this in one cycle with a appropriate directive? My read operation acctually needs 2 cycles.
12-04-2013 09:47 PM