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nanson
Explorer
Explorer
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Registered: ‎08-31-2017

Does VHLS provide the analysis of power estimation after enabling the adding a clock-enable port ( ap_ce ) to the design ?

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Hi, dear elites,

As far as I learn from the UG902, VHLS provides the directive to add a clock-enable port ( ap_ce ) to the design via the option -clock_enable in config_interface.

However, I'd like to inquire if the user adds the option, does VHLS provide the analysis of power estimation after asserting the input as high against low?  Or if the user would like to compare and analyze the effect of the input ce pin, what's your advise to estimate in Xilinx tool ?

Thanks

All the best,

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nupurs
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Registered: ‎06-24-2015

@nanson 

 

Refer this:
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0008-vivado-power-estimation-and-optimization-hub.html

Thanks,
Nupur
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nupurs
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Registered: ‎06-24-2015

@nanson 

 

Power analysis can only be done once the IP has been taken to Vivado.

Thanks,
Nupur
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
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nanson
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Registered: ‎08-31-2017

@nupurs 

Would you please suggest the related Xilinx document for further study? Thanks

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nupurs
Moderator
Moderator
1,091 Views
Registered: ‎06-24-2015

@nanson 

 

Refer this:
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0008-vivado-power-estimation-and-optimization-hub.html

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).

View solution in original post

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