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Observer
Observer
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Registered: ‎02-26-2020

Error generating IP for SYSGEN

Hello to Forum

After synthesis in Vivado HLS I am trying  exporting RTL as an IP for System Generator for DSP (Vivado) but get an error below

Error: [IMPL 213:65] C datatype is not supported

Any idea why?

Thanks in advance

Michael

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Moderator
Moderator
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Registered: ‎11-21-2018

Hi @misha2020 

It seems the error is pointing to a specific line of code? Can you post that? 
It seems like your using some kind of code that is not supported. 

Did C simulation/ synthetization fail with any errors?  

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎02-26-2020

Hi Aoife

Sorry for delay.

I redesigned my code and synthesized a core for Sysgen. Evidently, I do not have sufficient experience to understand what is a right code for IPs generation.

Concerning your question: the both C simulation/ synthetization finished without errors.

My question is :if exists a document that explains different  Vivado HLS messages, because the message that I received is difficult to understand:   " [IMPL 213:65] C datatype is not supported"  what does it mean?

Regards

Michael

 

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