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Registered: ‎08-25-2019

Error when running C/RTL cosimulation,UG871 interface synthesis lab1

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Version vivado HLS 2018.3,example is from lab1 of cha.4 interface synthesis in UG 871

C simulation and C synthesis run successfully and output the right reports. But error occurs when running C/RTL cosimulation. It should have output such a figure as below: 

1.JPG

But errors below: 

Starting C/RTL cosimulation ...
D:/Xilinx/Vivado/2018.3/bin/vivado_hls.bat D:/ug871-design-files/Interface_Synthesis/lab1/adders_prj/solution1/cosim.tcl
INFO: [HLS 200-10] Running 'D:/Xilinx/Vivado/2018.3/bin/unwrapped/win64.o/vivado_hls.exe'
INFO: [HLS 200-10] For user '123' on host '123-pc' (Windows NT_amd64 version 6.1) on Sun Aug 25 16:02:01 +0800 2019
INFO: [HLS 200-10] In directory 'D:/ug871-design-files/Interface_Synthesis/lab1'
INFO: [HLS 200-10] Opening project 'D:/ug871-design-files/Interface_Synthesis/lab1/adders_prj'.
INFO: [HLS 200-10] Opening solution 'D:/ug871-design-files/Interface_Synthesis/lab1/adders_prj/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.25ns.
INFO: [HLS 200-10] Setting target device to 'xc7a75tlftg256-2l'
ERROR: [COSIM 212-345] Cosim only supports the following 'ap_ctrl_none' designs: (1) combinational designs; (2) pipelined design with task inteveral of 1; (3) designs with array streaming or hls_stream or AXI4 stream ports.
command 'ap_source' returned error code
while executing
"source D:/ug871-design-files/Interface_Synthesis/lab1/adders_prj/solution1/cosim.tcl"
invoked from within
"hls::main D:/ug871-design-files/Interface_Synthesis/lab1/adders_prj/solution1/cosim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

Attached corresponding files, thanks!

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Moderator
Moderator
680 Views
Registered: ‎05-27-2018

Hi huangzhen18@foxmail.com ,

    I've recurrented your design, delete the line49, rerun the C synthesis and Cosim, then you will get the currect waveforms as posted above.

//#pragma HLS INTERFACE ap_ctrl_none port=return

   Because the default block-level I/O protocol is called ap_ctrl_hs. If you add the directive above, the block-level protocol is changed into ap_ctrl_none, which is not allow to be used in C/RTL cosimulation feature in HLS. Top-level function must be synthesized using an ap_ctrl_hs or ap_ctrl_chain blocklevel interface.

   In addition, ap_start, ap_done,ap_idle and ap_redy are ap_ctrl_hs block-level hand shake signals in the waveform. If you use ap_none, the signals would be different.
    ap_ctrl_hs.PNG

   Refer to UG902 page183 for more imformation.

Thanks,

Wen

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Highlighted
Moderator
Moderator
681 Views
Registered: ‎05-27-2018

Hi huangzhen18@foxmail.com ,

    I've recurrented your design, delete the line49, rerun the C synthesis and Cosim, then you will get the currect waveforms as posted above.

//#pragma HLS INTERFACE ap_ctrl_none port=return

   Because the default block-level I/O protocol is called ap_ctrl_hs. If you add the directive above, the block-level protocol is changed into ap_ctrl_none, which is not allow to be used in C/RTL cosimulation feature in HLS. Top-level function must be synthesized using an ap_ctrl_hs or ap_ctrl_chain blocklevel interface.

   In addition, ap_start, ap_done,ap_idle and ap_redy are ap_ctrl_hs block-level hand shake signals in the waveform. If you use ap_none, the signals would be different.
    ap_ctrl_hs.PNG

   Refer to UG902 page183 for more imformation.

Thanks,

Wen

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

View solution in original post

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Highlighted
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Registered: ‎08-25-2019

Thanks! My problem is solved.

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