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406 Views
Registered: ‎12-04-2018

Estimated clock period exceeds the target

Hi, I am new to FPGAs. Now I am using Vivado HLS 2017.4 to generate a IP than calling hls::FindStereoCorrespondenceBM for test, but csynth_design always reported "Estimated clock period (##ns) exceeds the target", could you tell me why and how to overcome these warnings? Thanks.

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3 Replies
Teacher xilinxacct
Teacher
377 Views
Registered: ‎10-23-2018

Re: Estimated clock period exceeds the target

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354 Views
Registered: ‎12-04-2018

Re: Estimated clock period exceeds the target

hi xilinxacct,
I have read this post and have tried similar modifications in FindStereoCorrespondenceBM:
change lines like:
int thresh = lminsad + (lminsad * state.uniquenessRatio / 100);
to:
int tmp_ls;
#pragma HLS RESOURCE variable=tmp_ls core=Mul
tmp_ls = lminsad * state.uniquenessRatio;
tmp_ls = tmp_ls / 100;
int thresh = lminsad + tmp_ls;

but the result does not change.

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Xilinx Employee
Xilinx Employee
308 Views
Registered: ‎09-05-2018

Re: Estimated clock period exceeds the target

puyou.lu@gmail.com,

If your design requirements allow for it, you can increase the target clock period under Solution->Solution Settings->Synthesis.

Nicholas Moellers

Xilinx Worldwide Technical Support
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