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Observer kevinnafs
Observer
10,424 Views
Registered: ‎01-15-2013

Export RTL VHDL(ISE) error

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Hello..

 

I was trying to export the RTL file, whit VHDL code to implement in a Zynq evaluation kit, but I'm not sure about what "format selection" I have to choose:

 

IP-XACT

System Generator for DSP(Vivado)

System Generator for DSP(ISE)

Pcore for EDK

 

I'd like to use the ISE Desing Suite 14.3 to make a testbench, so I've tried whit the "System Generator for DSP(ISE) option and got this error:

 

Export RTL ...
G:/Vivado/Vivado_HLS/2012.3/Win_x86/bin/vivado_hls_bin.exe -flow export -flow_args " -evaluate vhdl -format sysgen_ise "


@I [LIC-101] Checked out feature [VIVADO_HLS]
@W [HLS-40] Vivado and/or ISE in the PATH variable are not from the same build as Vivado HLS. The mismatch may result in unexpected behaviors.
@I [HLS-10] Running 'G:/Vivado/Vivado_HLS/2012.3/Win_x86/bin/vivado_hls_bin.exe'
@I [HLS-10] On platform 'Windows NT_intel version 5.1'
@I [HLS-10] Vivado HLS Tcl shell started on Wed Jan 16 00:36:09 -0400 2013 for user 'Pc' at host 'personal-4e79b2'
@I [HLS-10] Current directory: H:/Documentos/MarcoPracticoHLS/PrubeasHLS/MulMatFPnocuadMayor/matrizmul/solution1
@I [IMPL-8] Exporting RTL as an IP for System Generator for DSP (ISE).
@I [IMPL-264] Generating Xilinx FPU core: matrixmul1_ap_fadd_3_full_dsp
couldn't execute "coregen": no such file or directory

@E [IMPL-254] IP generation did not complete as expected.
@I [LIC-101] Checked in feature [VIVADO_HLS]

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1 Solution

Accepted Solutions
Explorer
Explorer
13,282 Views
Registered: ‎09-06-2012

Re: Export RTL VHDL(ISE) error

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Hi ,

 

Please review below few steps.

 

  1. First close the VHLS if it’s open.
  2. Set  the PATH variable (Right click My Computer > properties > Advance system settings > environment variable) to  C:\xilinx\vivado\tool_version\bin.
  3. Then try to open run the export RTL.

 

Please try this and let me know the outcome.

 

Ankury

 

 

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9 Replies
Observer kevinnafs
Observer
10,420 Views
Registered: ‎01-15-2013

Re: Export RTL VHDL(ISE) error

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Also I got this error during the Co-Simulation:
@I [SIM-12] Generating RTL test bench ...
@E [SIM-104] Cannot find Mentor Graphics ModelSim. Make sure it is accessible through the PATH variable.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

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Explorer
Explorer
10,403 Views
Registered: ‎09-06-2012

Re: Export RTL VHDL(ISE) error

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Hi,

 

as you are targetin to zynq so i would suggest you to go with Pocre for edk

 

1.click on export rtl.

2. go for "Pcore for EDk".

3.This will create one implementation folder in side your project directory.

....\solution1\impl\pcores\proj_name\synhdl\vhdl..

 

use this file to make a project in ISE or in vivado.

 

let me know the outcome

 

ANkury

 

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Explorer
Explorer
10,399 Views
Registered: ‎09-06-2012

Re: Export RTL VHDL(ISE) error

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Hi,

 

Regarding  the cosim error message i would suggest you to watch this video http://www.xilinx.com/training/vivado/verifying-your-vivado-hls-design.htm

 

ANkury 

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Observer kevinnafs
Observer
10,392 Views
Registered: ‎01-15-2013

Re: Export RTL VHDL(ISE) error

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Hi,

 

Ok I've tried whit the Pcore for EDK but I got this :

 

Export RTL ...
G:/Vivado/Vivado_HLS/2012.3/Win_x86/bin/vivado_hls_bin.exe -flow export -flow_args " -evaluate vhdl -format pcore  -version \"1.00.a\""
@I [LIC-101] Checked out feature [VIVADO_HLS]
@W [HLS-40] Vivado and/or ISE in the PATH variable are not from the same build as Vivado HLS. The mismatch may result in unexpected behaviors.
@I [HLS-10] Running 'G:/Vivado/Vivado_HLS/2012.3/Win_x86/bin/vivado_hls_bin.exe'
@I [HLS-10] On platform 'Windows NT_intel version 5.1'
@I [HLS-10] Vivado HLS Tcl shell started on Thu Jan 17 03:18:43 -0400 2013 for user 'Pc' at host 'personal-4e79b2'
@I [HLS-10] Current directory: H:/Documentos/MarcoPracticoHLS/PrubeasHLS/MulMatFP/matrizmul/solution1
@I [IMPL-8] Exporting the design as a Pcore for EDK.
@W [IMPL-380] Function protocol signals are direct connections in the resulting pcore. You may want to make them accessible by software using appropriate directives.
@I [IMPL-8] Starting RTL implementation using ISE ...
@E [IMPL-4] Cannot find ISE in the PATH variable or in this Xilinx software installation.
@I [LIC-101] Checked in feature [VIVADO_HLS

 

How can I change the PATH or configure it?. What happen if the Co-Simulation RTL didn't work before export the RTL file?.

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Explorer
Explorer
10,384 Views
Registered: ‎09-06-2012

Re: Export RTL VHDL(ISE) error

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Hi,

 

To perform RTL implementation, Vivado_HLs invoke Xilinx ISE tools. Therefore, the Xilinx ISE tools path must be known.

 

Please set the path for xilinx tool.

 

Ankury

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Observer kevinnafs
Observer
10,376 Views
Registered: ‎01-15-2013

Re: Export RTL VHDL(ISE) error

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Hi,

 

Thanks four your reply, I'm trying to set the path I found this in the preferences of Vivado HLS is that ok?.:

Path.JPG

 

Could you be more specific please?..

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Explorer
Explorer
13,283 Views
Registered: ‎09-06-2012

Re: Export RTL VHDL(ISE) error

Jump to solution

Hi ,

 

Please review below few steps.

 

  1. First close the VHLS if it’s open.
  2. Set  the PATH variable (Right click My Computer > properties > Advance system settings > environment variable) to  C:\xilinx\vivado\tool_version\bin.
  3. Then try to open run the export RTL.

 

Please try this and let me know the outcome.

 

Ankury

 

 

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Observer kevinnafs
Observer
10,351 Views
Registered: ‎01-15-2013

Re: Export RTL VHDL(ISE) error

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Hi,

 

Thanks!...this post help me a lot to solve the PATH problem whit ISE. But the PATH which worked was this one:

 

C:\xilinx\vivado\tool_version\bin\nt

 

 

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Visitor sandy111
Visitor
9,325 Views
Registered: ‎12-10-2013

Re: Export RTL VHDL(ISE) error

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i am getting this error when i try to export in Pcore. I have also added my path variables to 

C:\Xilinx\Vivado\2013.4\bin

but still i get this error,

 

@I [HLS-10] Setting target device to 'xc7z020clg484-1'
@E [IMPL-39] Cannot find ISE in the PATH variable or it's an unsupported version. Please update the PATH variable to include a supported version (13.1 and above)

while executing
"export_design -evaluate vhdl -format pcore -version "1.00.a" -use_netlist top"
(file "E:/xapp1167_vivado/test/solution1/export.tcl" line 8)
@I [LIC-101] Checked in feature [VIVADO_HLS]

----------------------------------------------------------------------------------------------------------

 

will be thankful if u can help me 

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