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shagarwal
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Registered: ‎09-26-2020

External Memory Access and Arrays

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Hi,

I had a few doubts/queries regarding external memory access (DDR3) and Array implementations in HLS.

1) If we define an array inside the top level function, that is implemented using BRAMs and LUTs. The accesses and clock sequencing is automatically taken care of. Is this correct ?

2) If we have an array as a top level function argument then it will result in creation of memory ports. Is the memory resource also automatically implemented by HLS using BRAMs and LUTs like previous case ?

3) How do I access an external DDR3 RAM from my custom IP ? How do I connect it to the memory ports implemented by top level function array type arguments ? How do I specify the Memory Offset ? How do I ensure proper synchronization ?

4) I wanted to create a simple design, where an Image is read from external DDR and some computations are performed by the custom IP. Finally the output image is again written back to the DDR. How can I implement this ?

 

Any help would be greatly appreciated. Thanks. 

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u4223374
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Registered: ‎04-26-2015

(1) Correct.

(2) No, in this case you need to connect an external BRAM (or LUT RAM) to the port on the HLS block.

(3) To do it all inside the HLS block, by far the easiest way is to specify the port with:

#pragma HLS INTERFACE m_axi port=<whatever> offset=<slave or direct>

This creates an AXI Master port on the block, which can be plugged into an AXI Slave port on either the Memory Interface Generator IP (which then talks to off-chip RAM) or the Zynq processing system (which has its own internal memory controller). Setting the offset to "slave" means that the base address in off-chip RAM shows up as a separate port (useful on Zynq, where you want the processor to set the offset), setting it to "direct" means that it'll be adjustable in the Vivado block design. Reads and writes on this array will access the off-chip RAM.

(4) See above. You just put an array as a top-level port, apply that pragma, and then read/write from the array. Note that DDR RAM is slow if you only read or write single elements at a time. It'll be much happier if you read maybe 16 - 256 elements into an internal BRAM buffer, process those, and then write them out. A well-designed block can interleave this so that while one set of data is being processed, the previous one is being written back to RAM and the next one is being read from RAM.

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u4223374
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Registered: ‎04-26-2015

(1) Correct.

(2) No, in this case you need to connect an external BRAM (or LUT RAM) to the port on the HLS block.

(3) To do it all inside the HLS block, by far the easiest way is to specify the port with:

#pragma HLS INTERFACE m_axi port=<whatever> offset=<slave or direct>

This creates an AXI Master port on the block, which can be plugged into an AXI Slave port on either the Memory Interface Generator IP (which then talks to off-chip RAM) or the Zynq processing system (which has its own internal memory controller). Setting the offset to "slave" means that the base address in off-chip RAM shows up as a separate port (useful on Zynq, where you want the processor to set the offset), setting it to "direct" means that it'll be adjustable in the Vivado block design. Reads and writes on this array will access the off-chip RAM.

(4) See above. You just put an array as a top-level port, apply that pragma, and then read/write from the array. Note that DDR RAM is slow if you only read or write single elements at a time. It'll be much happier if you read maybe 16 - 256 elements into an internal BRAM buffer, process those, and then write them out. A well-designed block can interleave this so that while one set of data is being processed, the previous one is being written back to RAM and the next one is being read from RAM.

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shagarwal
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Registered: ‎09-26-2020

Very Lucid explanation. I hope it will be helpful to others like me as well.

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