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Observer themoonboy
Observer
295 Views
Registered: ‎08-19-2019

Failed running C/RTL co-simulation

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Hi, I run SystemC-based program on Vivado HLS, the synthesis could proceed successfully, but when run C/RTL co-simulation, there always received a failed message:

 

Starting C/RTL cosimulation ...
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/bin/vivado_hls /home/zhaohan/Desktop/Vivado_HLS_projects/project1/solution1/cosim.tcl
INFO: [HLS 200-10] Running '/home/zhaohan/Desktop/Vivado/Vivado/2019.1/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'zhaohan' on host 'SEAS13440' (Linux_x86_64 version 5.0.0-29-generic) on Fri Oct 04 14:25:22 EDT 2019
INFO: [HLS 200-10] On os Ubuntu 18.04.3 LTS
INFO: [HLS 200-10] In directory '/home/zhaohan/Desktop/Vivado_HLS_projects'
Sourcing Tcl script '/home/zhaohan/Desktop/Vivado_HLS_projects/project1/solution1/cosim.tcl'
INFO: [HLS 200-10] Opening project '/home/zhaohan/Desktop/Vivado_HLS_projects/project1'.
INFO: [HLS 200-10] Opening solution '/home/zhaohan/Desktop/Vivado_HLS_projects/project1/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
WARNING: [HLS 200-40] Cannot find library '/home/zhaohan/Desktop/Vivado/Vivado/2019.1/common/technology/xilinx/Virtex-7/Virtex-7.lib'.
WARNING: [HLS 200-40] Cannot find library 'xilinx/Virtex-7/Virtex-7'.
INFO: [HLS 200-10] Setting target device to 'xc7vx485t-ffg1157-1'
INFO: [COSIM 212-2] Generating simulation wrapper in SystemC ...
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
Build using "/home/zhaohan/Desktop/Vivado/Vivado/2019.1/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling first_counter.cpp
Compiling first_counter_tb.cpp
Makefile.rules:409: recipe for target 'obj/first_counter_tb.o' failed
first_counter_tb.cpp: In function ‘int sc_main()’:
first_counter_tb.cpp:13:24: error: no match for call to ‘(sc_core::sc_in<sc_dt::sc_logic>) (sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>&)’
counter.reset(reset);
^
In file included from /home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_clock_ports.h:33:0,
from /home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/systemc:81,
from /home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/systemc.h:212,
from first_counter_tb.cpp:1:
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:758:10: note: candidate: void sc_core::sc_in<sc_dt::sc_logic>::operator()(const in_if_type&)
void operator () ( const in_if_type& interface_ )
^~~~~~~~
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:758:10: note: no known conversion for argument 1 from ‘sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>’ to ‘const in_if_type& {aka const sc_core::sc_signal_in_if<sc_dt::sc_logic>&}’
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:767:10: note: candidate: void sc_core::sc_in<sc_dt::sc_logic>::operator()(sc_core::sc_in<sc_dt::sc_logic>::in_port_type&)
void operator () ( in_port_type& parent_ )
^~~~~~~~
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:767:10: note: no known conversion for argument 1 from ‘sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>’ to ‘sc_core::sc_in<sc_dt::sc_logic>::in_port_type& {aka sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, (sc_core::sc_port_policy)0u>&}’
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:776:10: note: candidate: void sc_core::sc_in<sc_dt::sc_logic>::operator()(sc_core::sc_in<sc_dt::sc_logic>::inout_port_type&)
void operator () ( inout_port_type& parent_ )
^~~~~~~~
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:776:10: note: no known conversion for argument 1 from ‘sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>’ to ‘sc_core::sc_in<sc_dt::sc_logic>::inout_port_type& {aka sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, (sc_core::sc_port_policy)0u>&}’
first_counter_tb.cpp:14:26: error: no match for call to ‘(sc_core::sc_in<sc_dt::sc_logic>) (sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>&)’
counter.enable(enable);
^
In file included from /home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_clock_ports.h:33:0,
from /home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/systemc:81,
from /home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/systemc.h:212,
from first_counter_tb.cpp:1:
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:758:10: note: candidate: void sc_core::sc_in<sc_dt::sc_logic>::operator()(const in_if_type&)
void operator () ( const in_if_type& interface_ )
^~~~~~~~
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:758:10: note: no known conversion for argument 1 from ‘sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>’ to ‘const in_if_type& {aka const sc_core::sc_signal_in_if<sc_dt::sc_logic>&}’
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:767:10: note: candidate: void sc_core::sc_in<sc_dt::sc_logic>::operator()(sc_core::sc_in<sc_dt::sc_logic>::in_port_type&)
void operator () ( in_port_type& parent_ )
^~~~~~~~
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:767:10: note: no known conversion for argument 1 from ‘sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>’ to ‘sc_core::sc_in<sc_dt::sc_logic>::in_port_type& {aka sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, (sc_core::sc_port_policy)0u>&}’
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:776:10: note: candidate: void sc_core::sc_in<sc_dt::sc_logic>::operator()(sc_core::sc_in<sc_dt::sc_logic>::inout_port_type&)
void operator () ( inout_port_type& parent_ )
^~~~~~~~
/home/zhaohan/Desktop/Vivado/Vivado/2019.1/lnx64/tools/systemc/include/sysc/communication/sc_signal_ports.h:776:10: note: no known conversion for argument 1 from ‘sc_core::sc_signal<bool, (sc_core::sc_writer_policy)0u>’ to ‘sc_core::sc_in<sc_dt::sc_logic>::inout_port_type& {aka sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, (sc_core::sc_port_policy)0u>&}’
first_counter_tb.cpp:15:13: error: ‘struct ap_rtl::first_counter’ has no member named ‘counter_out’; did you mean ‘counter_out_i’?
counter.counter_out(counter_out);
^~~~~~~~~~~
make: *** [obj/first_counter_tb.o] Error 1
ERROR: [COSIM 212-317] C++ compile error.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-5] *** C/RTL co-simulation file generation failed. ***
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***
7
while executing
"source /home/zhaohan/Desktop/Vivado_HLS_projects/project1/solution1/cosim.tcl"
invoked from within
"hls::main /home/zhaohan/Desktop/Vivado_HLS_projects/project1/solution1/cosim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

 

And I attached my source code and testbench, both comes from SystemC official tutorial from ASIC world, and some bugs are fixed thus could successfully run synthesis.

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1 Solution

Accepted Solutions
Moderator
Moderator
138 Views
Registered: ‎11-21-2018

Re: Failed running C/RTL co-simulation

Jump to solution

Hi @themoonboy 

 

If you already have a solution for this could you update the community? 

Otherwise could you provide the extra files suggested by @shameera so we can help you solve this issue? 

 

Regards

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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2 Replies
Moderator
Moderator
207 Views
Registered: ‎05-31-2017

Re: Failed running C/RTL co-simulation

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Hi @themoonboy ,

It seems you have missed to attach the design files reproducing this issue.

So, can you please attach the design files this would help the community to provide any suggestions.

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Moderator
Moderator
139 Views
Registered: ‎11-21-2018

Re: Failed running C/RTL co-simulation

Jump to solution

Hi @themoonboy 

 

If you already have a solution for this could you update the community? 

Otherwise could you provide the extra files suggested by @shameera so we can help you solve this issue? 

 

Regards

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos