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milan_mian
Explorer
Explorer
10,548 Views
Registered: ‎11-21-2014

Field property mismatch. Value mismatch for: integer signed error during Vivado synthesis

Hi all,

 

I am novice in High level synthesis. I am trying color interpolation algorithm in HLS. My code is

 

typedef hls::stream<ap_axiu<8,1,1,1> >                AXI_STREAM_IN;
typedef hls::stream<ap_axiu<24,1,1,1> >               AXI_STREAM_OUT;

 

void Mod_CFA_Interpolation(AXI_STREAM_IN& src_axi, AXI_STREAM_OUT& dst_axi, int rows, int cols) {
#pragma HLS RESOURCE variable=src_axi core=AXIS metadata="-bus_bundle INPUT_STREAM"
#pragma HLS RESOURCE variable=dst_axi core=AXIS metadata="-bus_bundle OUTPUT_STREAM"
#pragma HLS INTERFACE ap_stable port=rows
#pragma HLS INTERFACE ap_stable port=cols

 

hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC1> img_0(rows, cols);
hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC3> img_1(rows, cols);


hls::Scalar<1, unsigned char> pix;
hls::Scalar<3, unsigned char> pixel;


hls::AXIvideo2Mat(src_axi, img_0);
unsigned char lineMemory[1920];

#pragma HLS RESOURCE variable=lineMemory core=RAM_2P
#pragma HLS ARRAY_PARTITION variable=lineMemory cyclic factor=2 dim=1

 

unsigned char buffer;

 

Rows:for(int i = 0; i < rows; i++)
     {
         Cols:for(int j = 0; j < cols; j++)

          {

           //Algorithm inside

          }

     }

hls::Mat2AXIvideo(img_1, dst_axi);

 

My Ip looks like this:

mod cfa.png

 

I get following error:

[xilinx.com:hls:Mod_CFA_Interpolation:1.0 311] /fmc_imageon_vita_color/Mod_CFA_Interpolation_0 INPUT_STREAM-TDATA&colon; Field property mismatch. Value mismatch for: integer signed. /fmc_imageon_vita_color/Mod_CFA_Interpolation_0 field: integer = false. /fmc_imageon_vita_color/v_vid_in_axi4s_0 video_out-TDATA field: rows_0_cols_0_Y = true.

 

[xilinx.com:hls:Mod_CFA_Interpolation:1.0 311] /fmc_imageon_vita_color/Mod_CFA_Interpolation_0 INPUT_STREAM-TDATA&colon; Field property mismatch. Value mismatch for: integer signed. /fmc_imageon_vita_color/Mod_CFA_Interpolation_0 field: integer = false. /fmc_imageon_vita_color/v_vid_in_axi4s_0 video_out-TDATA field: rows_0_cols_0_Y = true.

 

Please help.

 

 

 

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6 Replies
dahenk
Explorer
Explorer
10,521 Views
Registered: ‎09-02-2013

The inputs rows and cols aren't connected to anything. I suggest using a bus bundle to bundle them with the AXI Lite control bus. Using the directives copied from xapp1167:

#pragma HLS RESOURCE core=AXI_SLAVE variable=rows metadata="-bus_bundle CONTROL_BUS"
#pragma HLS RESOURCE core=AXI_SLAVE variable=cols metadata="-bus_bundle CONTROL_BUS"

#pragma HLS INTERFACE ap_stable port=rows
#pragma HLS INTERFACE ap_stable port=cols

and then you can set the rows/cols from the CPU through the M_AXI_GP connected to ap_ctrl interface (if you're using the Processing System IP and zynq) 

 

Or if you don't need to change image size on the fly, just remove the rows/cols inputs and set them statically like for example:

hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC1> img_0(1080, 1920);
hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC3> img_1(1080, 1920);

(Haven't tried it, but I think it works) 

 

Another thing: I recently noticed there is a hls::LineBuffer class that you might want to check out seeing as you made your custom line buffer. It comes with some build it shift functions.

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milan_mian
Explorer
Explorer
10,510 Views
Registered: ‎11-21-2014

Thanks dahenk. I tried your suggestions.Still, I get same errors; No difference.

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benzao
Observer
Observer
10,463 Views
Registered: ‎02-04-2014

I have same issue.

 

ben

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cousteau
Adventurer
Adventurer
5,760 Views
Registered: ‎05-11-2010

I just encountered this problem (except, in my case, when trying to output video).

 

It seems that:

  • The 8-bit data input of the HLS core is explicitly marked as unsigned.
  • The 8-bit data output of the Video In to Axi-4 Stream configured in Mono/Sensor mode is explicitly marked as signed.

I have no idea what this means (what does a bit array being "signed" mean? where can I change that? is there a sign conversion block or something like that? and most importantly, why is the monochrome video signal defined as "signed" and not "unsigned"?), but it seems to prevent this from being connected.

 

Some workarounds could be:

  • Make the HLS block input signed (ap_axis) rather than unsigned (ap_axiu), or alternatively just make a mini-block that converts from ap_axis to ap_axiu.  I don't know the implications of this though; I don't know if this would behave as expected or if values out of range would be cropped or result in some sort of undefined behavior.
  • Put an AXI4-Stream switch in the middle.  A previous design I made used a 1:2 switch upstream of the HLS block and a 2:1 switch downstream of it, so that the HLS block could be bypassed, and this somehow discards :

Untitled.png

  • Find a block that just removes the sign, as the switches do.  So far I've tried with the AXI4-Stream register slice, the FIFO, and even a simple vector slice applied to the tdata signal without success, so I ended up using the switches.  Now that I think of it maybe an AXI4-Stream Data Width Converter with same input and output widths was another possibility; could someone with this problem test that?
rappysaha
Adventurer
Adventurer
3,870 Views
Registered: ‎09-21-2016

Hello,

 

I have also faced this error. In my case, I have changed HLS block input ap_axiu to ap_axis. And my design is fully validated now. I am not sure about AXI_Switch function. But, I am not using AXI_Switch in my design.

 

Thank you

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wzj_153353
Newbie
Newbie
2,474 Views
Registered: ‎12-11-2017

Hello,

 

could you tell me how to change HLS block input ap_axiu to ap_axis  in detail? 

Because I tried to change ap_axiu to ap_axis in HLS, but AXIvideo2Mat just supports ap_axiu,  I tried to change some related functions but failed. 

 

Thank you!

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