cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
txu17
Visitor
Visitor
641 Views
Registered: ‎09-07-2020

Floating Point Unit in Vitis HLS

Jump to solution

Hi Folks,

I hope to learn more about how to use efficient (latency optimized) Floating Point implementations in Vitis HLS. Below are my questions, any feedback would be helpful!

1. In general, in Vitis, what is the correct approach to synthesize performant floating point computation implementations? Should we use the LogiCORE IP (https://www.xilinx.com/support/documentation/ip_documentation/floating_point/v7_1/pg060-floating-point.pdf)? Does it make a difference in Vitis and Vivado?
2. Is it possible to use the LogiCORE IP (https://www.xilinx.com/support/documentation/ip_documentation/floating_point/v7_1/pg060-floating-point.pdf) in Vitis? If so, is using the pragma bind_op the correct way to do so?

Thank you very much!

0 Kudos
1 Solution

Accepted Solutions
aoifem
Moderator
Moderator
519 Views
Registered: ‎11-21-2018

Hi @txu17 

 

I wrote some tutorials a while ago that are at quite an introductory level, so they should be ok for a beginner to follow. Tutorial 7 shows you how to export IP: 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-6-Introduction-to-AXI4-Lite-in-Vitis-HLS/ba-p/1137153

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-7-Connecting-to-the-PS-using-AXI4-Lite-and-Vitis-HLS/ba-p/1137753

 

Our docs on this are quite good as well: 

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/export_rtl_vitis_hls.html

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


**~ Got a minute? Answer our Vitis HLS survey here! ~**

**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

4 Replies
aoifem
Moderator
Moderator
539 Views
Registered: ‎11-21-2018

Hi @txu17 

It looks like the floating point IP is an IP core which you should use in Vivado, not Vivado HLS or Vitis HLS. I don't think it would be possible to export this IP from Vivado into Vitis HLS (although you can build an IP in Vitis HLS and export it into Vivado). If the core has all the functionality you need, I would advise against creating your own IP from scratch in Vitis HLS, to save development time. 

If you want to synthesize this core, I would look at the Vivado synthesis guide: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug896-vivado-ip.pdf

 

If you wish to create an IP from scratch in Vitis HLS, you can take a look at the functionality available in our libraries, to see if there are some functions which might help: 

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_ip_libraries.html

 

If you just wish too compare the results of creating an IP in Vitis HLS vs using a ready-made one in Vivado, you could use the floating point IP as a comparison. 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


**~ Got a minute? Answer our Vitis HLS survey here! ~**

**~ Don't forget to reply, give kudos, and accept as solution.~**
txu17
Visitor
Visitor
527 Views
Registered: ‎09-07-2020

Hi @aoifem

Thank you very much for the help and advice! This is very helpful. 

I would like to know could you elaborate more on how to build an IP in Vitis HLS and export it into Vivado? 
Since I a new to the Xilinx tools, could you point to an example project (of exporting Vitis HLS generated IP into Vivado) on the Xilinx GitHub repository (if there is any) or a specific section in the documentation? 
Thank you again! 


0 Kudos
aoifem
Moderator
Moderator
520 Views
Registered: ‎11-21-2018

Hi @txu17 

 

I wrote some tutorials a while ago that are at quite an introductory level, so they should be ok for a beginner to follow. Tutorial 7 shows you how to export IP: 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-6-Introduction-to-AXI4-Lite-in-Vitis-HLS/ba-p/1137153

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-7-Connecting-to-the-PS-using-AXI4-Lite-and-Vitis-HLS/ba-p/1137753

 

Our docs on this are quite good as well: 

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/export_rtl_vitis_hls.html

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


**~ Got a minute? Answer our Vitis HLS survey here! ~**

**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

txu17
Visitor
Visitor
510 Views
Registered: ‎09-07-2020

Hi @aoifem

Thank you very much! 

0 Kudos