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Explorer
Explorer
1,147 Views
Registered: ‎03-22-2017

Force stages into a pipeline

Given a pipelined loop (II=1) that iterates over few functions, is it possible to assign each function to a stage of the pipeline?

 

For example:

 

int par1, par2, par3, par4;

for (i = 0; i < N; i++) {
#pragma HLS PIPELINE II=1
  a(&par1, &par2);
  b(&par2, &par3);
  c(&par3, &par4);
}

Currently, no matter what I do, the iteration latency is 2 and II=1. Function a and b are scheduled in the same stage, while c has its own stage. I would like to have a stage for each of them. 

 

Do you have any suggestion?

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3 Replies
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Observer
Observer
1,063 Views
Registered: ‎12-28-2014

Hi,

I have a few suggestions in mind. You can try these and let me know if it helps

1. Try using the LATENCY directive. You can specify the desired latency number (in this case 3) and let the compiler see if it can understand. 

2. You can use ap_wait() statements in your code after each function invocation.

3. Maybe the compiler is inlining these functions and hence 'a' & 'b' are getting scheduled in the same iteration. Use #pragma HLS INLINE off directive for each function and see if the compiler understands.

 

Hope these help and let me know which one works for you.

 

--

Nikhil Pratap

 

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Explorer
Explorer
1,049 Views
Registered: ‎03-22-2017

@nikhilghanathe,

 

I am wondering if anyone - in particular from Xilinx - may help me on this.

 

Let me list my unsuccessful experiments. The final latency is always 2, while I am trying to force 3 (or more) clock cycles.

 

1) LATENCY directive does NOT really affect the latency.

 

I tried both:

 

int par1, par2, par3, par4;

PIPE: for (i = 0; i < N; i++) {
#pragma HLS PIPELINE II=1
#pragma HLS LATENCY min=3 max=3
  a(&par1, &par2);
  b(&par2, &par3);
  c(&par3, &par4);
}

and

 

 

int par1, par2, par3, par4;

PIPE: for (i = 0; i < N; i++) {
#pragma HLS PIPELINE II=1
  STAGE1: {
#pragma HLS LATENCY min=1 max=1
    a(&par1, &par2);
  }
  STAGE2: {
#pragma HLS LATENCY min=1 max=1
    b(&par2, &par3);
  }
  STAGE3: {
#pragma HLS LATENCY min=1 max=1
    c(&par3, &par4);
  }
}

 

 

2) According to the User Guide

  • ap_wait() should be used together with the PROTOCOL directive;
  • and both should be used ONLY for manually defining the scheduling of interfaces (and not the body of functions).

I tried them, in any case.

 

At first, I tried ap_wait() + PROTOCOL. But this returns the following WARNING and it ignores ap_wait().

 

WARNING: [SCHED 204-32] Invalid protocol: Cannot embed pipeline region inside protocol 'PIPE'.

 

 

 

#include <ap_utils.h>

int par1, par2, par3, par4;

PIPE: for (i = 0; i < N; i++) {
#pragma HLS PIPELINE II=1
#pragma HLS PROTOCOL fixed a(&par1, &par2); ap_wait(); b(&par2, &par3); ap_wait(); c(&par3, &par4); ap_wait(); }

 

Thus, I removed the PROTOCOL directive, but the ap_wait() are ignored as well.

 

 

#include <ap_utils.h>

int par1, par2, par3, par4;

for (i = 0; i < N; i++) {
#pragma HLS PIPELINE II=1
  a(&par1, &par2);
  ap_wait();
  b(&par2, &par3);
  ap_wait();
  c(&par3, &par4);
  ap_wait();
}

 

3) Finally, yes I made sure I was not inlining those function (INLINE off).

 

Do you have any other suggestion?

 

Thank you

 

 

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Observer
Observer
287 Views
Registered: ‎09-17-2018

@gdg 

Hi, I run into a similar issue like yours about handling the pipeline stage manually. Did you fix this issue or have any clue on this?

My problem is posted here: 

https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/How-to-set-up-a-manual-pipeline-force-pipeline-stages/td-p/1072052

Thank you in advance. 

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