11-29-2018 06:07 AM
can you please suggest me how to solve my problem? I have an AXI stream and when signaled I want to store accumulation of N frames (simply frame0 + frame1 + ... + frameN) to memory through AXI master.
I have a working solution (see attachment) but sometimes it can get stuck when there is other traffic on the same HP port to Zync PS (cosim is always alright). What is not good is the fact that it is reading and writing to memory all the time.
When I try to read/write to memory only if AXILite register is enabled HLS cannot perform the DATAFLOW optimization (see commented parts of top module).
Speed is not the issue here. I have also plenty of memory so it is even possible to store all N frames separately and when done add them together using PS. The only important thing is to keep AXI stream fluently running even when writing to memory.
Could I somehow solve it outside my IP using some kind of AXI stream switch to avoid unnecessary reads/writes?
Is there some directive how to avoid freezing when there is other communication on AXI master to the same HP port of PS? I tried limiting burst lenght and changing value of num_write_outstanding and num_read_outstanding but nothing helped.
Thank you for your comments
11-30-2018 02:23 AM
A few suggestions:
(1) Don't inline the functions; DATAFLOW works better when the function hierachy is preserved.
(2) Pass the "enabled" flag down into write_line, and use that to enable/disable the memcpy call. DATAFLOW does not deal well with having whole functions enabled/disabled; it does much better when the function just happens to take less time than normal (because it skipped a step). A lot of my functions just have a statement right at the start: "if (!enabled) return;" That way the function is always called, but often it just terminates straight away. In your case, I think you still need write_line to read the stream (to prevent the FIFO filling-up and deadlocking), but you don't have to write to RAM.
The other thing I'd mention is that it might be worth combining read_line and write_line into one function, re-using the same AXI Master - simply to ensure that the two masters aren't causing deadlocks in the AXI Infrastructure (eg. read_line starts a burst read, which then flows through into write_line. write_line tries to begin a burst write, but can't because the bus is occupied by read_line. So it stops, which stops the streams, which then stops read_line...).
12-06-2018 10:45 PM